參數(shù)資料
型號： XC3120A-3PC68C
廠商： Xilinx Inc
文件頁數(shù)： 49/76頁
文件大小： 0K
描述： IC LOGIC CL ARRAY 2000GAT 68PLCC
產品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標準包裝： 18
系列： XC3000A/L
LAB/CLB數(shù)： 64
RAM 位總計： 14779
輸入/輸出數(shù)： 58
門數(shù)： 1500
電源電壓： 4.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
供應商設備封裝： 68-PLCC
其它名稱： 122-1037
R
November 9, 1998 (Version 3.1)
7-55
XC3000 Series Field Programmable Gate Arrays
7
XC3100A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes: 1. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
2. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and
0.30 ns (-09).
Speed Grade
-4-3-2-1
-09
Description
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Combinatorial Delay
Logic Variables
A, B, C, D, E,
to outputs X or Y
1TILO
3.3
2.7
2.2
1.75
1.5
ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive
X or Y
8TCKO
TQLO
2.5
5.2
2.1
4.3
1.7
3.5
1.4
3.1
1.25
2.7
ns
Set-up time before clock K
Logic Variables
A, B, C, D, E
Data In
DI
Enable Clock
EC
Reset Direct inactive
RD
2
4
6
TICK
TDICK
TECCK
2.5
1.6
3.2
1.0
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
1.7
1.2
2.3
1.0
1.5
1.0
2.05
1.0
ns
Hold Time after clock K
Logic Variables
A, B, C, D, E
Data In
DI
Enable Clock
EC
3
5
7
TCKI
TCKDI
TCKEC
0
1.0
0.8
0
0.9
0.7
0
0.9
0.7
0
0.8
0.6
0
0.7
0.55
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
TCH
TCL
FCLK
2.0
227
1.6
270
1.3
323
1.3
323
1.3
370
ns
MHz
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
13
9
TRPW
TRIO
3.2
3.7
2.7
3.1
2.3
2.7
2.3
2.4
2.05
2.15
ns
Global Reset (RESET Pad)1
RESET width (Low)
(XC3142A)
delay from RESET pad to outputs X or Y
TMRW
TMRQ
14.0
12.0
ns
Prelim
Product Obsolete or Under Obsolescence
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