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參數(shù)資料
| 型號： | XC3120A-3PC68C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 36/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LOGIC CL ARRAY 2000GAT 68PLCC |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 64 |
| RAM 位總計： | 14779 |
| 輸入/輸出數(shù)： | 58 |
| 門數(shù)： | 1500 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC |
| 其它名稱： | 122-1037 |
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R
November 9, 1998 (Version 3.1)
7-43
XC3000 Series Field Programmable Gate Arrays
7
XC3000A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes: 1. Timing is based on the XC3042A, for other devices see timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
Speed Grade
-7
-6
Description
Symbol
Min
Max
Min
Max
Units
Combinatorial Delay
Logic Variables
A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
1TILO
5.1
5.6
4.1
4.6
ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
8TCKO
TQLO
4.5
9.5
10.0
4.0
8.0
8.5
ns
Set-up time before clock K
Logic Variables
A, B, C, D, E
FG Mode
F and FGM Mode
Data In
DI
Enable Clock
EC
2
4
6
TICK
TDICK
TECCK
4.5
5.0
4.0
4.5
3.5
4.0
3.0
4.0
ns
Hold Time after clock K
Logic Variables
A, B, C, D, E
Data In
DI2
Enable Clock
EC
3
5
7
TCKI
TCKDI
TCKEC
0
1.0
2.0
0
1.0
2.0
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
TCH
TCL
FCLK
4.0
113.0
3.5
135.0
ns
MHz
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
13
9
TRPW
TRIO
6.0
5.0
ns
Global Reset (RESET Pad)1
RESET width (Low)
delay from RESET pad to outputs X or Y
TMRW
TMRQ
16.0
19.0
14.0
17.0
ns
Product Obsolete or Under Obsolescence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3120A-3PC68I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-3PC84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-3PC84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-3PQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-3PQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
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