- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4176 > XC3090A-7PC84C (Xilinx Inc)IC LOGIC CL ARRAY 9000GAT 84PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3090A-7PC84C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 76/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LOGIC CL ARRAY 9000GAT 84PLCC |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 320 |
| RAM 位總計(jì)： | 64160 |
| 輸入/輸出數(shù)： | 70 |
| 門數(shù)： | 6000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC |
| 其它名稱： | 122-1034 XC3090A-7PC84C-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁當(dāng)前第76頁
R
November 9, 1998 (Version 3.1)
7-11
XC3000 Series Field Programmable Gate Arrays
7
General Purpose Interconnect
General purpose interconnect, as shown in Figure 10, con-
sists of a grid of five horizontal and five vertical metal seg-
ments located between the rows and columns of logic and
IOBs. Each segment is the height or width of a logic block.
Switching matrices join the ends of these segments and
allow programmed interconnections between the metal grid
segments of adjoining rows and columns. The switches of
an unprogrammed device are all non-conducting. The con-
nections through the switch matrix may be established by
the automatic routing or by selecting the desired pairs of
matrix pins to be connected or disconnected. The legiti-
mate switching matrix combinations for each pin are indi-
cated in Figure 11.
Special buffers within the general interconnect areas pro-
vide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bidi)
buffers are found adjacent to the switching matrices, above
and to the right. The other PIPs adjacent to the matrices
are accessed to or from Longlines. The development sys-
tem automatically defines the buffer direction based on the
location of the interconnection network source. The delay
calculator of the development system automatically calcu-
lates and displays the block, interconnect and buffer delays
for any paths selected. Generation of the simulation netlist
with a worst-case delay model is provided.
Direct Interconnect
Direct interconnect, shown in Figure 12, provides the most
efficient implementation of networks between adjacent
CLBs or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the B input of the CLB immediately to its right and to the C
input of the CLB to its left. The Y output can use direct inter-
connect to drive the D input of the block immediately above
and the A input of the block below. Direct interconnect
should be used to maximize the speed of high-performance
portions of logic. Where logic blocks are adjacent to IOBs,
direct connect is provided alternately to the IOB inputs (I)
and outputs (O) on all four edges of the die. The right edge
provides additional direct connects from CLB outputs to
adjacent IOBs. Direct interconnections of IOBs with CLBs
are shown in Figure 13.
D
Q
D
Q
D
Q
Count Enable
Parallel Enable
Clock
D2
D1
D0
Dual Function of 4 Variables
Function of 6 Variables
Function of 5 Variables
Q2
Q1
Q0
FG
Mode
F
Mode
FGM
Mode
Terminal
Count
X5383
Figure 7: Counter.
The modulo-8 binary counter with parallel enable and
clock enable uses one combinatorial logic block of each
option.
Figure 8: A Design Editor view of routing resources
used to form a typical interconnection network from
CLB GA.
Product Obsolete or Under Obsolescence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3064A-7PC84C | IC LOGIC CL ARRAY 6400GAT 84PLCC |
| XC3064A-7PQ160C | IC LOGIC CL ARRAY 6400GAT 160PQF |
| ASC49DRYH-S93 | CONN EDGECARD 98POS DIP .100 SLD |
| AMC44DRTI-S13 | CONN EDGECARD 88POS .100 EXTEND |
| AMC44DREI-S13 | CONN EDGECARD 88POS .100 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3090A-7PC84C0090 | 制造商:Xilinx 功能描述: |
| XC3090A7PC84I | 制造商:XIL 功能描述:3090A7PC XILINX'95 |
| XC3090A-7PC84I | 制造商:XIL 功能描述:3090A7PC XILINX'95 制造商:Xilinx 功能描述: |
| XC3090A-7PC84I0100 | 制造商:Xilinx 功能描述: |
| XC3090A-7PG175C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。