The memory cell outputs Q and Q use ground and V<" />
參數(shù)資料
型號： XC3030A-7PC44C
廠商： Xilinx Inc
文件頁數(shù)： 45/76頁
文件大?。?/td> 0K
描述： IC LOGIC CL ARRAY 3000GAT 44PLCC
標準包裝： 26
系列： XC3000A/L
LAB/CLB數(shù)： 100
RAM 位總計： 22176
輸入/輸出數(shù)： 34
門數(shù)： 2000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
供應商設(shè)備封裝： 44-PLCC（16.59x16.59）
其它名稱： 122-1017
R
November 9, 1998 (Version 3.1)
7-7
XC3000 Series Field Programmable Gate Arrays
7
The memory cell outputs Q and Q use ground and VCC lev-
els and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing infor-
mation, embedded in the program data by the development
system, to direct memory-cell loading. The serial-data
framing and length-count preamble provide programming
compatibility for mixes of various FPGA device devices in a
synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in Figure 4, provides an
interface between the external package pin of the device
and the internal user logic. Each IOB includes both regis-
tered and direct input paths. Each IOB provides a program-
mable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
Q
Data
Read or
Write
Configuration
Control
Q
X5382
Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and con-
trols one program selection in the Field Programmable
Gate Array.
FLIP
FLOP
Q
D
R
SLEW
RATE
PASSIVE
PULL UP
OUTPUT
SELECT
3-STATE
INVERT
OUT
INVERT
FLIP
FLOP
or
LATCH
D
Q
R
REGISTERED IN
DIRECT IN
OUT
3- STATE
(OUTPUT ENABLE)
TTL or
CMOS
INPUT
THRESHOLD
OUTPUT
BUFFER
(GLOBAL RESET)
CK1
X3029
I/O PAD
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
PROGRAMMABLE INTERCONNECTION POINT or PIP
=
IK
OK
Q
I
O
T
PROGRAM
CONTROLLED
MULTIPLEXER
CK2
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.
A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
XC3020A-7PC84C IC LOGIC CL ARRAY 2000GAT 84PLCC
ASM43DTMS-S189 CONN EDGECARD 86POS R/A .156 SLD
XC3030A-7PC84C IC LOGIC CL ARRAY 3000GAT 84PLCC
AGM43DTMS-S189 CONN EDGECARD 86POS R/A .156 SLD
AYM43DTBS-S189 CONN EDGECARD 86POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3030A-7PC44I 制造商:Xilinx 功能描述:
XC3030A-7PC68C 制造商:Xilinx 功能描述:
XC3030A-7PC68C0090 制造商:Xilinx 功能描述:
XC3030A-7PC68C0100 制造商:Xilinx 功能描述:
XC3030A-7PC68C0236 制造商:Xilinx 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*