參數(shù)資料
型號: XC2S200E-6PQG208C
廠商: Xilinx Inc
文件頁數(shù): 66/108頁
文件大小: 0K
描述: IC SPARTAN-IIE FPGA 200K 208PQFP
標準包裝: 24
系列: Spartan®-IIE
LAB/CLB數(shù): 1176
邏輯元件/單元數(shù): 5292
RAM 位總計: 57344
輸入/輸出數(shù): 146
門數(shù): 200000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1324
60
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O (CS),
L5P_YY
1
P112
All
-
I/O (WRITE),
L5N_YY
1
P113
All
-
I/O
1
P114
-
I/O, VREF
Bank 1
1
P115
-
All
I/O
1
P116
-
I/O, L4P_YY
1
P117
All
XC2S100E
I/O, L4N_YY
1
P118
All
-
GND
-
P119
-
VCCINT
-
P120
-
I/O, L3P_YY
1
P121
All
-
I/O, L3N_YY
1
P122
All
-
I/O, VREF
Bank 1
1
P123
-
All
I/O
1
P124
-
I/O (DLL), L2P
1
P125
-
GCK2, I
1
P126
-
GND
-
P127
-
VCCO
-
P128
-
GCK3, I
0
P129
-
VCCINT
-
P130
-
I/O (DLL), L2N
0
P131
-
I/O, VREF
Bank 0
0
P132
-
All
I/O, L1P_YY
0
P133
All
-
0
P134
All
-
VCCINT
-
P135
-
GND
-
P136
-
I/O, L0P_YY
0
P137
All
-
I/O, L0N_YY
0
P138
All
XC2S100E
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
I/O
0
P139
-
I/O, VREF
Bank 0
0
P140
-
All
I/O
0
P141
-
I/O
0
P142
-
TCK
-
P143
-
VCCO
-
P144
-
TQ144 Differential Clock Pins
Clock
Bank
P
N
Pin
Name
Pin
Name
GCK0
4
P55
GCK0, I
P56
I/O (DLL),
L17P
GCK1
5
P52
GCK1, I
P50
I/O (DLL),
L17N
GCK2
1
P126
GCK2, I
P125
I/O (DLL),
L2P
GCK3
0
P129
GCK3, I
P131
I/O (DLL),
L2N
TQ144 Pinouts (XC2S50E and XC2S100E)
(Continued)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
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