參數(shù)資料
型號(hào)： XC2S200E-6PQG208C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 60/108頁(yè)
文件大?。?/td> 0K
描述： IC SPARTAN-IIE FPGA 200K 208PQFP
標(biāo)準(zhǔn)包裝： 24
系列： Spartan®-IIE
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計(jì)： 57344
輸入/輸出數(shù)： 146
門(mén)數(shù)： 200000
電源電壓： 1.71 V ~ 1.89 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
其它名稱(chēng)： 122-1324
DS077-4 (v3.0) August 9, 2013
55
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Spartan-IIE Package Pinouts
The Spartan-IIE family of FPGAs is available in five popu-
lar, low-cost packages, including plastic quad flat packs and
fine-pitch ball grid arrays. Family members have footprint
compatibility across devices provided in the same package,
with minor exceptions due to the smaller number of I/O in
smaller devices or due to LVDS/LVPECL pin pairing. The
Spartan-IIE family is not footprint compatible with any other
FPGA family. The following package-specific pinout tables
indicate function, pin, and bank information for all devices
available in that package. The pinouts follow the pad loca-
tions around the die, starting from pin 1 on the QFP pack-
ages.
Package Overview
Table 12 shows the five low-cost, space-saving production
package styles for the Spartan-IIE family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “TQ144” package becomes
“TQG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx sales for more information.
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in Table 13.
For additional package information, see UG112: Device
Package User Guide.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Material Declaration Data Sheets (MDDS) are also
available on the Xilinx web site for each package.
Table 12: Spartan-IIE Family Package Options
Package
Leads
Type
Maximum
I/O
Lead Pitch
(mm)
Footprint
Area (mm)
Height
(mm)
Mass(1)
(g)
TQ144 / TQG144
144
Thin Quad Flat Pack (TQFP)
102
0.5
22 x 22
1.60
1.4
PQ208 / PQG208
208
Plastic Quad Flat Pack (PQFP)
146
0.5
30.6 x 30.6
3.70
5.3
FT256 / FTG256
256
Fine-pitch Thin Ball Grid Array (FBGA)
182
1.0
17 x 17
1.55
1.0
FG456 / FGG456
456
Fine-pitch Ball Grid Array (FBGA)
329
1.0
23 x 23
2.60
2.2
FG676 / FGG676
676
Fine-pitch Ball Grid Array (FBGA)
514
1.0
27 x 27
2.60
3.1
Notes:
1.
Package mass is
±10%.
Table 13: Xilinx Package Documentation
Package
Drawing
MDDS
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG456
FGG456
FG676
FGG676
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S200E-6PQG208I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-IIE FPGA
XC2S200E-6TQ144C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-IIE 1.8V FPGA Family
XC2S200E-6TQ144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-IIE 1.8V FPGA Family
XC2S200E-6TQG144C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-IIE FPGA
XC2S200E-6TQG144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-IIE FPGA
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