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參數資料
| 型號： | XC2S200E-6PQG208C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 24/108頁 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-IIE FPGA 200K 208PQFP |
| 標準包裝： | 24 |
| 系列： | Spartan®-IIE |
| LAB/CLB數： | 1176 |
| 邏輯元件/單元數： | 5292 |
| RAM 位總計： | 57344 |
| 輸入/輸出數： | 146 |
| 門數： | 200000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 122-1324 |
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22
DS077-2 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Signals
There are two kinds of pins that are used to configure
Spartan-IIE devices: Dedicated pins perform only specific
configuration-related functions; the other pins can serve as
general purpose I/Os once user operation has begun.
The dedicated pins comprise the mode pins (M2, M1, M0),
the configuration clock pin (CCLK), the PROGRAM pin, the
DONE pin and the boundary-scan pins (TDI, TDO, TMS,
TCK). Depending on the selected configuration mode,
CCLK may be an output generated by the FPGA, or may be
generated externally, and provided to the FPGA as an input.
Note that some configuration pins can act as outputs. For
correct operation, these pins require a VCCO of 3.3V to drive
an LVTTL signal or 2.5V to drive an LVCMOS signal. All the
relevant pins fall in banks 2 or 3. The CS and WRITE pins
for Slave Parallel mode are located in bank 1.
For a more detailed description than that given below, see
the Spartan-II and Spartan-IIE FPGA Families.
The Process
The sequence of steps necessary to configure Spartan-IIE
devices are shown in Figure 16. The overall flow can be
divided into three different phases.
Initiating configuration
Configuration memory clear
Loading data frames
Start-up
The memory clearing and start-up phases are the same for
all configuration modes; however, the steps for the loading
of data frames are different. Thus, the details for data frame
loading are described separately in the sections devoted to
each mode.
Initiating Configuration
There are two different ways to initiate the configuration pro-
cess: applying power to the device or asserting the PRO-
GRAM input.
Configuration on power-up occurs automatically unless it is
delayed by the user, as described in a separate section
below. The waveform for configuration on power-up is
Before configuration can begin, VCCO Bank 2 must be
greater than 1.0V. Furthermore, all VCCINT power pins must
be connected to a 1.8V supply. For more information on
delaying configuration, see Clearing Configuration Memory,
Once in user operation, the device can be re-configured
simply by pulling the PROGRAM pin Low. The device
acknowledges the beginning of the configuration process by
driving DONE Low, then enters the memory-clearing phase.
Table 11: Configuration Modes
Configuration Mode
Preconfiguration
Pull-ups
M0
M1
M2
CCLK
Direction
Data Width
Serial DOUT
Master Serial mode
No
0
Out
1
Yes
0
1
Slave Parallel mode
(SelectMAP)
Yes
0
1
0
In
8
No
0
1
Boundary-Scan mode
Yes
1
0
N/A
1
No
1
0
1
Slave Serial mode
Yes
1
0
In
1
Yes
No
1
Notes:
1.
During power-on and throughout configuration, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os
(those not assigned signals) will remain in a high-impedance state. Pins used as outputs may pulse High at the end of configuration
(see Answer 10504).
2.
If the Mode pins are set for preconfiguration pull-ups, those resistors go into effect once the rising edge of INIT samples the Mode
pins. They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine
whether the unused I/Os have a pull-up, pull-down, or no resistor.
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