參數(shù)資料
型號(hào)： XC2S200E-6PQG208C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 35/108頁(yè)
文件大小： 0K
描述： IC SPARTAN-IIE FPGA 200K 208PQFP
標(biāo)準(zhǔn)包裝： 24
系列： Spartan®-IIE
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計(jì)： 57344
輸入/輸出數(shù)： 146
門(mén)數(shù)： 200000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
其它名稱： 122-1324
32
DS077-3 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Recommended Operating Conditions
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Max
Units
TJ
Junction temperature
Commercial
0
85
°C
Industrial
–40
100
°C
VCCINT
Supply voltage relative to GND(1)
Commercial
1.8 – 5%
1.8 + 5%
V
Industrial
1.8 – 5%
1.8 + 5%
V
VCCO
Supply voltage relative to GND(2)
Commercial
1.2
3.6
V
Industrial
1.2
3.6
V
TIN
Input signal transition time(3)
-
250
ns
Notes:
1.
Functional operation is guaranteed down to a minimum VCCINT of 1.62V (Nominal VCCINT –10%). For every 50 mV reduction in
VCCINT below 1.71V (nominal VCCINT –5%), all delay parameters increase by approximately 3%.
2.
Minimum and maximum values for VCCO vary according to the I/O standard selected.
3.
Input and output measurement threshold is ~50% of VCCO. See Delay Measurement Methodology, page 41 for specific details.
Symbol
Description
Min
Typ
Max
Units
VDRINT
Data retention VCCINT voltage (below which configuration data may
be lost)
1.5
-
V
VDRIO
Data retention VCCO voltage (below which configuration data may be
lost)
1.2
-
V
ICCINTQ
Quiescent VCCINT supply current(1)
XC2S50E
Commercial
-
10
200
mA
Industrial
-
10
200
mA
XC2S100E
Commercial
-
10
200
mA
Industrial
-
10
200
mA
XC2S150E
Commercial
-
10
300
mA
Industrial
-
10
300
mA
XC2S200E
Commercial
-
10
300
mA
Industrial
-
10
300
mA
XC2S300E
Commercial
-
12
300
mA
Industrial
-
12
300
mA
XC2S400E
Commercial
-
15
300
mA
Industrial
-
15
300
mA
XC2S600E
Commercial
-
15
400
mA
Industrial
-
15
400
mA
ICCOQ
Quiescent VCCO supply current(1)
-
2
mA
IREF
VREF current per VREF pin
-
20
μA
IL
Input or output leakage current per pin
–10
-
+10
μA
CIN
Input capacitance (sample tested)
TQ, PQ, FG, FT packages
-
8
pF
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
(sample tested)(2)
-
0.25
mA
IRPD
Pad pull-down (when selected) @ VIN = 3.6V (sample tested)(2)
-
0.25
mA
Notes:
1.
With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2.
Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not provide valid logic levels when input pins are connected to other circuits.
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