參數(shù)資料
型號: XC2S200E-6PQ208C
廠商: Xilinx Inc
文件頁數(shù): 49/108頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V 1176 CLB'S 208-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: Spartan®-IIE
LAB/CLB數(shù): 1176
邏輯元件/單元數(shù): 5292
RAM 位總計: 57344
輸入/輸出數(shù): 146
門數(shù): 200000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1209
DS077-3 (v3.0) August 9, 2013
45
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Symbol
Description
Speed Grade
Units
-7
-6
Min
Max
Min
Max
Combinatorial Delays
TILO
4-input function: F/G inputs to X/Y outputs
0.18
0.42
0.18
0.47
ns
TIF5
5-input function: F/G inputs to F5 output
0.3
0.8
0.3
0.9
ns
TIF5X
5-input function: F/G inputs to X output
0.3
0.8
0.3
0.9
ns
TIF6Y
6-input function: F/G inputs to Y output via F6 MUX
0.3
0.9
0.3
1.0
ns
TF5INY
6-input function: F5IN input to Y output
0.04
0.2
0.04
0.22
ns
TIFNCTL
Incremental delay routing through transparent latch to
XQ/YQ outputs
-
0.7
-
0.8
ns
TBYYB
BY input to YB output
0.18
0.46
0.18
0.51
ns
Sequential Delays
TCKO
FF clock CLK to XQ/YQ outputs
0.3
0.9
0.3
1.0
ns
TCKLO
Latch clock CLK to XQ/YQ outputs
0.3
0.9
0.3
1.0
ns
Setup/Hold Times with Respect to Clock CLK
TICK / TCKI
4-input function: F/G inputs
1.0 / 0
-
1.1 / 0
-
ns
TIF5CK / TCKIF5
5-input function: F/G inputs
1.4 / 0
-
1.5 / 0
-
ns
TF5INCK / TCKF5IN 6-input function: F5IN input
0.8 / 0
-
0.8 / 0
-
ns
TIF6CK / TCKIF6
6-input function: F/G inputs via F6 MUX
1.5 / 0
-
1.6 / 0
-
ns
TDICK / TCKDI
BX/BY inputs
0.7 / 0
-
0.8 / 0
-
ns
TCECK / TCKCE
CE input
0.7 / 0
-
0.7 / 0
-
ns
TRCK / TCKR
SR/BY inputs (synchronous)
0.52 / 0
-
0.6 / 0
-
ns
Clock CLK
TCH
Pulse width, High
1.3
-
1.4
-
ns
TCL
Pulse width, Low
1.3
-
1.4
-
ns
Set/Reset
TRPW
Pulse width, SR/BY inputs
2.1
-
2.4
-
ns
TRQ
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
0.3
0.9
0.3
1.0
ns
FTOG
Toggle frequency (for export control)
-
400
-
357
MHz
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