參數(shù)資料
型號(hào)： XC2S100E-6FTG256C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 32/108頁(yè)
文件大小： 0K
描述： IC SPARTAN-IIE FPGA 100K 256FBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-IIE
LAB/CLB數(shù)： 600
邏輯元件/單元數(shù)： 2700
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 182
門(mén)數(shù)： 100000
電源電壓： 1.71 V ~ 1.89 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
其它名稱(chēng)： 122-1322
DS077-1 (v3.0) August 9, 2013
3
Product Specification
2001–2013 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Introduction
The Spartan-IIE Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
seven-member family offers densities ranging from 50,000
to 600,000 system gates, as shown in Table 1. System per-
formance is supported beyond 200 MHz.
Features include block RAM (to 288K bits), distributed RAM
(to 221,184 bits), 19 selectable I/O standards, and four
DLLs (Delay-Locked Loops). Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy
development
cycles,
and
inherent
risk
of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
Second generation ASIC replacement technology
-
Densities as high as 15,552 logic cells with up to
600,000 system gates
-
Streamlined features based on Virtex-E FPGA
architecture
-
Unlimited in-system reprogrammability
-
Very low cost
-
Cost-effective 0.15 micron technology
System level features
-
SelectRAM hierarchical memory:
16 bits/LUT distributed RAM
Configurable 4K-bit true dual-port block RAM
Fast interfaces to external RAM
-
Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
-
Low-power segmented routing architecture
-
Dedicated carry logic for high-speed arithmetic
-
Efficient multiplier support
-
Cascade chain for wide-input functions
-
Abundant registers/latches with enable, set, reset
-
Four dedicated DLLs for advanced clock control
Eliminate clock distribution delay
Multiply, divide, or phase shift
-
Four primary low-skew global clock distribution nets
-
IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
-
Pb-free package options
-
Low-cost packages available in all densities
-
Family footprint compatibility in common packages
-
19 high-performance interface standards
LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
LVDS and LVPECL differential I/O
-
Up to 205 differential I/O pairs that can be input,
output, or bidirectional
-
Hot swap I/O (CompactPCI friendly)
Core logic powered at 1.8V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx ISE development
system
-
Fully automatic mapping, placement, and routing
-
Integrated with design entry and verification tools
-
Extensive IP library including DSP functions and
soft processors
Spartan-IIE FPGA Family:
Introduction and Ordering
Information
DS077-1 (v3.0) August 9, 2013
0
Product Specification
R
Table 1: Spartan-IIE FPGA Family Members
Device
Logic
Cells
Typical
System Gate Range
(Logic and RAM)
CLB
Array
(R x C)
Total
CLBs
Maximum
Available
User I/O(1)
Maximum
Differential
I/O Pairs
Distributed
RAM Bits
Block RAM
Bits
XC2S50E
1,728
23,000 - 50,000
16 x 24
384
182
83
24,576
32K
XC2S100E
2,700
37,000 - 100,000
20 x 30
600
202
86
38,400
40K
XC2S150E
3,888
52,000 - 150,000
24 x 36
864
265
114
55,296
48K
XC2S200E
5,292
71,000 - 200,000
28 x 42
1,176
289
120
75,264
56K
XC2S300E
6,912
93,000 - 300,000
32 x 48
1,536
329
120
98,304
64K
XC2S400E
10,800
145,000 - 400,000
40 x 60
2,400
410
172
153,600
160K
XC2S600E
15,552
210,000 - 600,000
48 x 72
3,456
514
205
221,184
288K
Notes:
1.
User I/O counts include the four global clock/user input pins. See details in Table 2, page 5
相關(guān)PDF資料
PDF描述
ACB91DHFT-S621 EDGECARD 182POS SMD W/O POST
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ACB91DHFT-S578 EDGECARD 182POS .050 SMD W/POSTS
XC2S100E-6FT256C IC FPGA 1.8V 600 CLB'S 256-FBGA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S100E-6FTG256I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-IIE FPGA
XC2S100E-6PQ208C 功能描述:IC FPGA 1.8V 600 CLB'S 208-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門(mén)數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S100E-6PQ208I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-IIE FPGA
XC2S100E-6PQG208C 功能描述:IC FPGA 1.8V 600 CLB'S 208-PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門(mén)數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S100E-6PQG208I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-IIE FPGA
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