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參數(shù)資料
| 型號： | X96012V14IZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 傳感器調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | 2 線 |
| 電流 - 電源： | 15mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
13
FN8216.3
February 20, 2008
Voltage Reference
The voltage reference to the A/D and D/A converters on the
X96012, may be driven from the on-chip voltage reference,
or from an external source via the VREF pin. Bit VRM in
Control Register 0 selects between the two options. See
Figure 5.
The default value of VRM is “0”, which selects the internal
reference. When the internal reference is selected, it’s
output voltage is also an output at pin VREF with a nominal
value of 1.21 V. If an external voltage reference is preferred,
the VRM bit of the Control Register 0 must be set to “1”.
A/D Converter
The X96012 contains a general purpose, on-chip, 8-bit
Analog to Digital (A/D) converter whose output is available at
the Status Register as bits AD[7:0]. By default these output
bits are used to select a row in the look-up tables associated
with the X96012’s Current Generators. When bit ADCfiltOff
is “0” (default), bits AD[7:0] are updated each time the ADC
performs four consecutive conversions with the same exact
result at the 6 MSBs. When bit ADCfiltOff is “1”, these bits
are updated after every ADC conversion.
A block diagram of the A/D converter is shown in Figure 6.
The voltage reference input (see “Voltage Reference” on
page 13), sets the maximum amplitude of the ramp
generator output. The A/D converter input signal (see “A/D
Converter Input Select” on page 13 for details) is compared
to the ramp generator output. The control and encode logic
produces a binary encoded output, with a minimum value of
00h (010), and a full scale output value of FFh (25510).
The A/D converter input voltage range (VINADC) is from 0V
to V(VREF).
A/D Converter Input Select
The input signal to the A/D converter on the X96012, may be
the output of the on-chip temperature sensor, or an external
source via the VSENSE pin. Bit ADCIN in Control register 0
selects between the two options. See Figure 7. It’s default
value is “0”, which selects the internal temperature sensor.
If an external source is intended as the input to the A/D
converter, the ADCIN bit of the Control register 0 must be set
to “1”.
A/D Converter Range
From Figure 6 we can see that the operating range of the
A/D converter input depends on the voltage reference. And
from Figure 7 we see that the internal temperature Sensor
output also varies with the voltage reference (VREF).
Table 4 summarizes the voltage range restrictions on the
VSENSE and VREF pins in different configurations.
VRM: BIT 2 IN CONTROL REGISTER 0
VREF PIN
ON-CHIP
A/D CONVERTER AND
VOLTAGE
REFERENCE
D/A CONVERTERS REFERENCE
FIGURE 5. VOLTAGE REFERENCE STRUCTURE
TABLE 4. VSENSE AND VREF RANGES
VREF
A/D CONVERTER INPUT
RANGES
Internal
Internal Temp Sensor
Not Applicable
Internal
VSense Pin
0
≤ V(VSense) ≤
V(VREF)
External
VSense Pin
0
≤ V(VREF) ≤ 1.3 V
0
≤ V(VSense) ≤V(VREF)
External
Internal Temp. Sensor
Not a Valid Case
All voltages referred to VSS
RAMP
GENERATOR
A/D CONVERTER INPUT
FROM VREF
CLOCK
CONTROL AND
ENCODE LOGIC
CONVERSION RESET
A/D CONVERTER
OUTPUT
(TO LUTS
AND STATUS
REGISTER)
8
COMPARATOR
VSENSE
ON-CHIP
TO A/D
ADCIN: BIT 3 IN CONTROL REGISTER 0.
TEMPERATURE
SENSOR
PIN
VREF
CONVERTER
INPUT
FIGURE 7. A/D CONVERTER INPUT SELECT STRUCTURE
X96012
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