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參數(shù)資料
| 型號： | X96012V14IZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 傳感器調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | 2 線 |
| 電流 - 電源： | 15mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
18
FN8216.3
February 20, 2008
X96012 Memory Map
The X96012 contains a 2176 bit array of mixed volatile and
nonvolatile memory. This array is split up into four distinct
parts, namely: (Refer to Figure 15).
General Purpose Memory (GPM)
Look-up Table 1 (LUT1)
Look-up Table 2 (LUT2)
Control and Status Registers
The GPM is all nonvolatile EEPROM, located at memory
addresses 00h to 7Fh.
The Control and Status registers of the X96012 are used in
the test and setup of the device in a system. These registers
are realized as a combination of both volatile and nonvolatile
memory. These registers reside in the memory locations 80h
through 8Fh. The reserved bits within registers 80h through
86h, must be written as “0” if writing to them, and should be
ignored when reading. The reserved registers, from 88h
through 8Fh, must not be written, and their content should
be ignored.
Both look-up tables LUT1 and LUT2 are realized as
non-volatile EEPROM, and extend from memory locations
90h - CFh and D0h - 10Fh respectively. These look-up tables
are dedicated to storing data solely for the purpose of setting
the outputs of Current Generators I1 and I2 respectively.
All bits in both look-up tables are preprogrammed to “0” at the
factory.
Addressing Protocol Overview
All Serial Interface operations must begin with a START,
followed by a Slave Address Byte. The Slave address
selects the X96012, and specifies if a Read or Write
operation is to be performed.
It should be noted that the Write Enable Latch (WEL) bit must
first be set in order to perform a Write operation to any other bit.
communication to the X96012 over the 2-wire serial bus is
conducted by sending the MSB of each byte of data first.
Even though the 2176 bit memory consists of four differing
functions, it is physically realized as one contiguous array,
organized as 17 pages of 16 bytes each.
The X96012 2-wire protocol provides one address byte,
therefore, only 256 bytes can be addressed directly. The
next few sections explain how to access the different areas
for reading and writing.
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER
0
7
LOOK-UP TABLE 2
(LUT2)
ADDRESS
SIZE
64 BYTES
16 BYTES
128 BYTES
10FH
00H
7FH
80H
8FH
90H
CFH
D0H
FFH
LOOK-UP TABLE 1
(LUT1)
CONTROL AND STATUS
REGISTERS
GENERAL PURPOSE
MEMORY (GPM)
FIGURE 15. X96012 MEMORY MAP
SA6
SA7
SA5
SA3
SA2
SA1
SA0
DEVICE TYPE
IDENTIFIER
READ OR
SA4
SLAVE ADDRESS
BIT(S)
DESCRIPTION
SA7 - SA4
Device Type Identifier
SA3 - SA1
Device Address
SA0
Read or Write Operation Select
R/W
10
1
0
ADDRESS
DEVICE
AS0
AS1
AS2
WRITE
FIGURE 16. SLAVE ADDRESS (SA) FORMAT
X96012
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