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參數(shù)資料
| 型號(hào)： | XA2C32A-7VQG44Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD 32MCELL 33 I/O 44-VQFP |
| 產(chǎn)品培訓(xùn)模塊： | CoolRunner-II CPLD Starter Kit |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 5.5ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 2 |
| 宏單元數(shù)： | 32 |
| 門數(shù)： | 750 |
| 輸入/輸出數(shù)： | 33 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-VQFP（10x10） |
| 包裝： | 托盤 |
DS552 (v1.1) May 5, 2007
1
Product Specification
2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
Guaranteed to meet full electrical specifications over
TA = -40° C to +105° C with TJ Maximum = +125° C
(Q-grade)
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
-
Optimized architecture for effective logic synthesis
-
Multi-voltage I/O operation: 1.5V through 3.3V
Available in Pb-free 44-pin VQFP with 33 user I/O
Advanced system features
-
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
-
IEEE1149.1 JTAG Boundary Scan Test
-
Optional Schmitt-trigger input (per pin)
-
Two separate I/O banks
-
RealDigital 100% CMOS product term generation
-
Flexible clocking modes
Optional DualEDGE triggered registers
-
Global signal options with macrocell control
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
-
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
-
Advanced design security
-
Open-drain output option for Wired-OR and LED
drive
-
Optional configurable grounds on unused I/Os
-
Optional bus-hold, 3-state or weak pullup on
selected I/O pins
-
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
-
PLA architecture
Superior pinout retention
100% product term routability across function
block
-
Hot pluggable
Refer to the CoolRunner-II Automotive CPLD family data
sheet for architecture description.
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The CoolRunner-II Automotive 32-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved
This device consists of two Function Blocks interconnected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
The CoolRunner-II Automotive 32-macrocell CPLD is I/O
compatible with standard LVTTL and LVCMOS18,
LVCMOS25, and LVCMOS33 (see Table 1). This device is
also 1.5V I/O compatible with the use of Schmitt-trigger
inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II Auto-
motive 32-macrocell device that permit easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V devices.
0
XA2C32A CoolRunner-II
Automotive CPLD
DS552 (v1.1) May 5, 2007
00
Product Specification
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