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參數(shù)資料
| 型號： | X96012V14IZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/23頁 |
| 文件大小： | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 傳感器調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | 2 線 |
| 電流 - 電源： | 15mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
10
FN8216.3
February 20, 2008
L1DA5 - L1DA0: LUT1 DIRECT ACCESS BITS
When bit L1DAS (bit 4 in Control register 5) is set to “1”,
LUT1 is addressed by these six bits, and it is not addressed
by the output of the on-chip A/D converter. When bit L1DAS
is set to “0”, these six bits are ignored by the X96012. See
Figure 10.
A value between 00h (0010) and 3Fh (6310) may be written to
these register bits, to select the corresponding row in LUT1.
The written value is added to the base address of LUT1
(90h).
Control Register 2
This register is accessed by performing a read or write
operation to address 82h of memory. This byte’s volatility is
determined by bit NV1234 in Control register 0.
L2DA5 - L2DA0: LUT2 DIRECT ACCESS BITS
When bit L2DAS (bit 6 in Control register 5) is set to “1”,
LUT2 is addressed by these six bits, and it is not addressed
by the output of the on-chip A/D converter. When bit L2DAS
is set to “0”, these six bits are ignored by the X96012. See
Figure 10.
A value between 00h (0010) and 3Fh (6310) may be written to
these register bits, to select the corresponding row in LUT2.
The written value is added to the base address of LUT2
(D0h).
Control Register 3
This register is accessed by performing a Read or Write
operation to address 83h of memory. This byte’s volatility is
determined by bit NV1234 in Control register 0.
D1DA7 - D1DA0: D/A 1 DIRECT ACCESS BITS
When bit D1DAS (bit 5 in Control register 5) is set to “1”, the
input to the D/A converter 1 is the content of bits D1DA7 -
D1DA0, and it is not a row of LUT1. When bit D1DAS is set
to “0” (default) these eight bits are ignored by the X96012.
See Figure 9.
X96012
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