參數(shù)資料
型號(hào)： X9520
英文描述： Triple DCP, POR, 2 kbit EEPROM Memory, Dual Voltage Monitors(3個(gè)DCP,上電復(fù)位,2k位串行EEPROM,分別的雙電壓監(jiān)控器端電壓-1.0~+15V)
中文描述： 三氯酚，葡萄牙，2千比特EEPROM存儲(chǔ)器，雙電壓監(jiān)視器（3個(gè)副處長(zhǎng)，上電復(fù)位和2K位串行EEPROM中，分別的雙電壓監(jiān)控器端電壓-1.0?15V的）
文件頁(yè)數(shù)： 14/34頁(yè)
文件大?。?/td> 210K
代理商： X9520
REV 1.3 4/13/04
Characteristics subject to change without notice.
14 of 34
www.xicor.com
X9520
– Preliminary Information
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1 and
BL0 bits written to the CONSTAT register. It is possible to
lock the regions of EEPROM memory shown in the table
below:
If the user attempts to perform a write operation on a pro-
tected region of EEPROM memory, the operation is
aborted without changing any data in the array.
When the Block Lock bits of the CONSTAT register are
set to something other than BL1=0 and BL0=0, then the
“wiper position” of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:
The factory default setting for these bits are BL1 = 0, BL0
= 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9520 is active (HIGH), then all nonvolatile write opera-
tions to both the EEPROM memory and DCPs are inhib-
ited, irrespective of the Block Lock bit settings (See "WP:
Write Protection Pin").
POR1, POR0: Power On Reset bits – (Nonvolatile)
Applying voltage to V
CC
activates the Power On Reset cir-
cuit which holds V1RO output HIGH, until the supply volt-
age stabilizes above the V
TRIP1
threshold for a period of
time, t
PURST
(See Figure 30).
The Power On Reset bits, POR1 and POR0 of the CON-
STAT register determine the t
PURST
delay time of the
Power On Reset circuitry (See "VOLTAGE MONITORING
FUNCTIONS"). These bits of the CONSTAT register are
nonvolatile, and therefore power up to the last written
state.
The nominal Power On Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
The default for these bits are POR1 = 0, POR0 = 1.
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power up the VxOS (x=2,3) bits default to the value “0”.
These bits can be set to a “1” by writing the appropriate
value to the CONSTAT register. To provide consistency
between the VxRO and VxOS however, the status of the
VxOS bits can only be set to a “1” when the correspond-
ing VxRO output is HIGH.
BL1
BL0
Protected Addresses
(Size)
Partition of array
locked
0
0
None (Default)
None (Default)
0
1
C0h - FFh
(64 bytes
)
Upper 1/4
1
0
80h - FFh
(128 bytes
)
Upper 1/2
1
1
00h - FFh
(256 bytes)
All
BL1
BL0
DCP Write Operation Permissible
0
0
YES (Default)
0
1
NO
1
0
NO
1
1
NO
POR1
POR0
Power on Reset delay (t
PUV1RO
)
50ms
0
0
0
1
100ms (Default)
1
0
200ms
1
1
300ms
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
C
K
1
1
1
1
1
1
1
1
A
C
K
SCL
SDA
S
T
O
P
A
C
K
CS7 CS6CS5 CS4 CS3 CS2CS1 CS0
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 18. CONSTAT Register Write Command Sequence
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