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參數(shù)資料
| 型號： | X9470 |
| 廠商： | Intersil Corporation |
| 英文描述： | RF Power Amplifier (PA) Bias Controller |
| 中文描述： | 射頻功率放大器（PA）的偏置控制器 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 542K |
| 代理商： | X9470 |
PeimnayInomaion
put that is used to drive the gate of an LDMOS transis-
tor.
Preliminary Information
X9470
16 of 25
REV 11.16 3/20/03
www.xicor.com
Figure 5. Operating modes X9470
When no RF signal is present, the instrumentation
amplifier of the X9470 senses the drain current as a
voltage drop,
V, across an external drain R
sense
resis-
tor. The
V is amplified and compared to an external
scaling voltage, V
REF
. Any difference between
V and
V
REF
results in a resistive increment or decrement of
the internal R
BIAS
potentiometer.
The R
BIAS
potentiometer is used as a voltage divider
with the RH
BIAS
and RL
BIAS
terminals setting the
upper and lower voltage limits of the unbuffered
RW
BIAS
voltage. The resolution of the R
BIAS
potenti-
ometer resistor is 0.4% of the difference of voltage
across the RH
BIAS
and RL
BIAS
terminals. The R
TOTAL
is typically 10K
with 256-taps. So, for example, if the
difference between the RH
BIAS
and RL
BIAS
terminals
is 1.024V, then the step accuracy is 4mV.
The voltage at the RW
BIAS
pin is then fed into the
V
BIAS
voltage follower. The V
BIAS
pin is a buffered out-
The scaling voltage, V
REF
, set by the R
REF
potentiom-
eter, sets the calibrated operating point of the LDMOS
Amplifier.
On edge transitions of the INC/DEC signal, the X9470 will
latch the current wiper position—this is known as “Bias
Lock” mode. This is shown in Figure 6. When BiasLock
occurs, the comparator hysteresis will allow INC/DEC to
change state only after the IA output changes by more
than 20mV. This will prevent toggling of the V
BIAS
output
unless the drain bias current is constantly changing.
State 2: DC-bias Disable When RF is Present
(optional)
When an RF signal is present, the X9470 is put into
standby mode (open loop). The X9470 is in standby
mode when the CS pin is disabled so that the R
BIAS
potentiometer holds the last wiper position. The pres-
ence of an RF signal at the input of a Class A or AB
amplifier increases the current across the R
sense
resis-
tor. Over a period of time, the temperature of the
LDMOS also increases and the LDMOS also experi-
ences V
GS
drift. Therefore the DC biasing point that
was set during State 1 (calibration) is not optimal.
Adjustments to the gate voltage will need to be made
to optimize the operation of the LDMOS PA. This is
done in State 3.
Choose Vref to scale IDQ, perform calibration,
Latch bias point for DC bias current in wiper counter
State 1
State 2
State 3
State 4
PA
Transmit Mode
PA
Calibration Mode
PA
Standby Mode
PA
Off Mode
Disable Bias Adjustment,
Recalibrate bias point for drift and temperature.
Rbias resistor will automatically increment or decrement
for optimal operating point continuously
Turn off PA
PA Enabled, Vout and INC/DEC Monitored for status
State 0
PA
Monitor Mode
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