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參數(shù)資料
| 型號(hào)： | X9470 |
| 廠商： | Intersil Corporation |
| 英文描述： | RF Power Amplifier (PA) Bias Controller |
| 中文描述： | 射頻功率放大器（PA）的偏置控制器 |
| 文件頁(yè)數(shù)： | 14/25頁(yè) |
| 文件大?。?/td> | 542K |
| 代理商： | X9470 |
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The WEL bit may be reset afterwards to prevent further
NV writes.
Preliminary Information
X9470
14 of 25
REV 11.16 3/20/03
www.xicor.com
Figure 3. Bias Adjustment Block Diagram
NON-VOLATILE STORE OF THE BIAS POSITION
The following procedure will store the values for the
Rref and Rbias wiper positions in Non-Volatile memory.
This sequence is intended to be performed after a
BiasLock calibration sequence to simplify storage. If
BiasLock has not been achieved, then the Rbias wiper
position may change when the CS pin is brought high
and SCL begins clocking. See Figure 4 for the actual
sequence.
1. Set the WEL bit with a write command (02h to regis-
ter 0Fh)
2. Peform a calibration and achieve BiasLock. Leave
CS pin high.
3. Write the address byte only (START, followed by
device/slave address and a 0 for a write, see page
20).
4. Perform a STOP command.
5. With SCL still low, bring the CS low. The falling edge
of the CS will initiate the NV write.
INC/DEC FUNCTION
The INC/DEC pin is an open-drain logic output that
tracks the activity of the increment/decrement compar-
ator. A logic HIGH at INC/DEC indicates that the I
DQ
did not rise up to the desired setting indicated by V
REF
while a logic LOW at the INC/DEC pin indicates that
the IDQ is higher than the desired setting.
INC/DEC is used as an internal control signal as well.
As an example, when INC/DEC is LOW, the Bias
Adjustment Circuit Block will start to move the Rbias
resistor wiper towards the RL
BIAS
terminal end when
CS is HIGH and SCL is clocking. Consequently, the
V
BIAS
voltage will decrease, and the I
DQ
decreases to
meet the desired V
REF
setting.
The INC/DEC signal can also be used to detect a dam-
aged RF power FET. For instance, If INC/DEC stays
HIGH during and after a calibration sequence it may
indicate that the RF power FET has failed. This indica-
tor can also be used with a level sense on the V
OUT
pin
to perform diagnostics.
SHUTDOWN MECHANISM
This hardware control shutdown pin (SHDN) will pull
the voltage of V
BIAS
to VSS with an internal pull down
resistor. When shutdown is disabled (V
BIAS
is active
when SHDN is LOW), the V
BIAS
voltage will move to
the previous desired bias voltage.
It will take less than a microsecond to enable the inter-
nal output buffer depending on the loading condition at
the V
BIAS
pin.
Gate Bias
Op Amp
–
+
RW
BIAS
RH
BIAS
RL
BIAS
Legend
External pin/signal
Internal node/signal
SCL
CS
2
3
1
V
BIAS
(unbuffered)
V
BIAS
SHDN
to LDMOS gate
10Kohm
256-tap
R
BIAS
INC
U/D
CS
INC/DEC
Note:
1) WCR = Wiper Control Register
XDCP
Memory and Control
WCR (Rbias)
Bias Register
non-volatile
Power On Recall
(POR)
INC/DEC is logic HIGH or LOW
from Sense/Scale Block
and is used to increment or
decrement the Rbias resistor
(XDCP) to adjust the gate voltage.
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