參數(shù)資料
型號(hào)： X9470
廠商： Intersil Corporation
英文描述： RF Power Amplifier (PA) Bias Controller
中文描述： 射頻功率放大器（PA）的偏置控制器
文件頁(yè)數(shù)： 10/25頁(yè)
文件大?。?/td> 542K
代理商： X9470
PeimnayInomaion
interface. CS must be low for this function.
Preliminary Information
X9470
10 of 25
REV 11.16 3/20/03
www.xicor.com
DETAILED PIN DESCRIPTIONS
Supply Pins
Digital Supplies VCC, VSS
The positive power supply and ground for the DCP dig-
ital control sections. VSS is normally tied to digital
ground. The X9470 is provided with separate digital
and analog power supply pins to better isolate digital
noise from the analog section.
Analog Supplies V+, AGND
The positive analog supply and ground for the Instru-
mentation Amplifier (IA). The analog supply ground is
kept separate to allow an external single point connec-
tion. V+ can be a separate supply voltage from VCC, or
VCC can be filtered before connection to V+.
Bias Adjustment Circuit Block Pins
RH
BIAS
, RL
BIAS
, and RW
BIAS
for
VBIAS Adjust-
ments.
These pins are the connections to a Xicor Digitally
Controlled Potentiometer (XDCP
TM
) or R
BIAS
potenti-
ometer. RH
BIAS
is connected to the most positive refer-
ence, and the RL
BIAS
is connected to the least positive
reference voltage. The potentiometer has a resolution
of 256-taps and typical R
TOTAL
of 10kohm. So for
example, to provide 4mV resolution, the voltage differ-
ence applied to the RH
BIAS
and RL
BIAS
pins must be
1.024V. The RW
BIAS
value can be stored in non-vola-
tile memory and recalled upon power up.
Serial Clock (SCL).
This is a dual function input pin. The state of the CS pin
determines the functionality.
Function 1:
SCL
is a negative edge-triggered control
pin of the R
BIAS
potentiometer. Toggling
SCL
will
either increment or decrement the wiper in the
direction indicated by the logic level on the INC/DEC
pin. CS must be high for this function.
Function 2: SCL is the serial bus clock for serial bus
Chip Select (CS). Calibration Enable.
The CS input is the enable bias adjustments. When the
CS is HIGH (enabled) and a SCL pulse is present, the
wiper position on the R
BIAS
potentiometer will auto-
matically update with either an increment or decrement
the comparator.
When CS is LOW (disabled), the wiper counter of the
XDCP will hold the last wiper position until CS is
enabled again and the wiper position is updated.
INC/DEC Monitor Pin
The Up or Down Monitor pin (INC/DEC) indicates the
state of the comparator. This signal indicates that the
Instrumentation Amplifier output voltage is higher or
lower than the voltage level set by the RW
REF
pin. The
output is used to indicate the direction that the gate
bias voltage needs to move to reach the target bias
voltage.
Sense and Scale Block Pins
V
SENSE+
and V
SENSE-
These are the input pins to the IA circuit. These pins
are used to determine the change in voltage across the
the external drain sense resistor of an RF power ampli-
fier.
RH
REF
, RL
REF
, and RW
REF
. PA Bias Set Point.
The PA Bias reference voltage is controlled by a 64-tap
(10k ohm typical R
TOTAL
) potentiometer, called the
R
REF
potentiometer. The voltages applied to RH
REF
and RL
REF
will determine the range of adjustment of
the reference voltage level (VREF) for the Comparator.
The resolution of the comparator reference is the differ-
ence of the voltages applied to RH
REF
and RL
REF
divided by 63. The position of the wiper (RW
REF
) is
controlled via serial bus. The RW
REF
value can be
stored in non-volatile memory and recalled upon power
up.
RW
REF
is also an input signal used as a scaling volt-
age (VREF) to set the appropriate I
DQ
of an RF power
amplifier. V
REF
can be derived from an external voltage
divider or from a baseband processor or similar micro-
controller. V
REF
can be set permanently or changed
dynamically using the potentiometer for various PA
operating points.
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