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參數(shù)資料
| 型號(hào)： | X25385 |
| 英文描述： | Selectable Timeout Watchdog & V CC Supervisory Circuit w/Serial E 3 PROM(可選超時(shí)看門(mén)狗監(jiān)控電路) |
| 中文描述： | 可選的超時(shí)看門(mén)狗 |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 90K |
| 代理商： | X25385 |
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X25383/85
2
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present on
the SI pin are latched on the rising edge of the clock input,
while data on the SO pin change after the falling edge of
the clock input.
Chip Select (CS)
When CS is HIGH, the device is deselected and the SO
output pin is at high impedance and unless a nonvolatile
write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device, placing it in
the active power mode. It should be noted that after
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the device are
disabled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is still
LOW will interrupt a write to the device. If the internal write
cycle has already been initiated, WP going low will have
no affect on this write.
Reset (RESET/RESET)
RESET/RESET is an active LOW/HIGH, open drain out-
put which goes active whenever Vcc falls below the mini-
mum Vcc sense level V
trip
. It will remain active until Vcc
rises above the minimum Vcc sense level for 200ms.
RESET/RESET will also go active if the Watchdog Timer
is enabled and CS remains either HIGH or LOW longer
than the selectable Watchdog time-out period. A falling
edge of CS will reset the Watchdog Timer.
PIN CONFIGURATION
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
V
SS
V
CC
RESET/RESET
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Reset Output
8 Lead SOIC
X25383/85
CS
SO
WP
VSS
1
2
3
4
RESET/RESET
SCK
SI
8
7
6
5
VCC
0.197”
0.244”
Not to Scale
SCK
SI
VSS
WP
VCC
CS
SO
1
2
3
4
8
7
6
5
8 Lead TSSOP
X25383
0.122"
0.252"
RESET/RESET
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X25385S8 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25385S8-1.8 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25385S8-2.7 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25385S8I | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25385S8I-1.8 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:SPI Serial EEPROM with Supervisory Features |
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