參數(shù)資料
型號: X25640
英文描述: Advanced SPI Serial E2PROM With Block LockTM Protection
中文描述: 先進(jìn)的SPI串行E2PROM保護(hù)帶座LockTM
文件頁數(shù): 1/14頁
文件大?。?/td> 64K
代理商: X25640
X25640
1
64K
X25640
8K x 8 Bit
Xicor, Inc. 1994, 1995, 1996 Patents Pending
3089-1.8 6/17/96 T4/C4/D1 NS
Characteristics subject to change without notice
Direct Write and Block Lock Protection is a trademark of Xicor, Inc.
Advanced SPI Serial E
2
PROM With Block Lock
TM
Protection
DESCRIPTION
The X25640 is a CMOS 65,536-bit serial E
2
PROM,
internally organized as 8K x 8. The X25640 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (
CS
) input, allowing any
number of devices to share the same bus.
The X25640 also features two additional inputs that
provide the end user with added flexibility. By asserting
the
HOLD
input, the X25640 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The
WP
input can be used as a hardwire input
to the X25640 disabling all write attempts to the status
register, thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25640 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
FEATURES
1MHz Clock Rate
Low Power CMOS
—200
μ
A Standby Current
—5mA Active Current
5 Volt Power Supply
SPI Modes (0,0 & 1,1)
8K X 8 Bits
—32 Byte Page Mode
Block Lock Protection
—Protect 1/4, 1/2 or all of E
2
PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
8-Lead PDlP Package
14-Lead SOIC Package
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
TIMING
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
8K BYTE
ARRAY
64 X 256
Y DECODE
DATA REGISTER
SO
SI
SCK
CS
HOLD
WP
64
128
8
32
STATUS
REGISTER
64
128 X 256
64 X 256
3089 ILL F01
A
PPLICATION
N
OTES
A V A I L A B L E
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