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參數(shù)資料
| 型號： | X1242 |
| 英文描述： | Real Time Clock/Calendar/Alarms/CPU Supervisor(實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/帶EEPROM的監(jiān)控) |
| 中文描述： | 實(shí)時(shí)時(shí)鐘/日歷/報(bào)警/ CPU監(jiān)控（實(shí)時(shí)時(shí)鐘/日歷/鬧鐘/帶EEPROM中的監(jiān)控） |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 119K |
| 代理商： | X1242 |
X1242 – Preliminary Information
Characteristics subject to change without notice.
10 of 24
REV 1.1.3 10/15/00
www.xicor.com
Figure 11. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
– The 2nd Data Byte of a Status Register Write Oper-
ation (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Figure 12. Acknowledge Response From Receiver
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
WRITE OPERATIONS
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers” on page 6.)
Upon receipt of each address byte, the X1242
responds with an acknowledge. After receiving both
address bytes the X1242 awaits the eight bits of data.
After receiving the 8 data bits, the X1242 again
responds with an acknowledge. The master then ter-
minates the transfer by generating a stop condition.
The X1242 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 13.
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