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參數(shù)資料
| 型號： | X1203 |
| 英文描述： | 2-Wire RTC(Real Time Clock)/Calendar/Alarm(實時時鐘/日歷/警報) |
| 中文描述： | 2線實時時鐘（實時時鐘）/日歷/鬧鐘（實時時鐘/日歷/警報） |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 84K |
| 代理商： | X1203 |
X1203
9
Figure 6. Byte Write Sequence
Figure 7. Page Write Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
CCR
Address 1
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
A
C
K
CCR
Address 0
1
1
1
1
0
1
1
0 0 0 0 0 0 0 0
CRR
Address 0
S
t
a
r
t
S
t
o
p
Slave
Address
CCR
Address 1
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1
<
n
<
8)
1
1
1
1
0
1
1
0 0 0 0 0 0 0 0
After the receipt of each byte, the X1203 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. If the master supplies
more than 8 bytes of data, then the previously loaded
data is over written by the new data, one byte at a
time. The master terminates the Data Byte loading by
issuing a stop condition, which causes the device to
begin the non volatile write cycle. As with the byte
write operation, all inputs are disabled until completion
of the internal write cycle. Refer to Figure 7 for the
address, acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Acknowledge Polling
The disabling of the inputs during non volatile write
cycles can be used to take advantage of the typical
5mS write cycle time. Once the stop condition is
issued to indicate the end of the master’s byte load
operation, the device initiates the internal non volatile
write cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a start con-
dition followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the non
volatile write cycle then no ACK will be returned. If the
device has completed the write operation, an ACK will
be returned and the host can then proceed with the
read or write operation. Refer to the flow chart in Figure 8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| x1205(中文) | Real Time Clock/Calendar(實時時鐘/日期) |
| X1205V8 | Real Time Clock/Calendar |
| X1205V8I | Real Time Clock/Calendar |
| X1205 | Real Time Clock/Calendar |
| X1205S8 | Real Time Clock/Calendar |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X1203S8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-SMD-RTC WITH EEPROM |
| X1203S8I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| X1203V8 | 制造商:Intersil Corporation 功能描述: |
| X-120-499 | 制造商:Brady Corporation 功能描述:VIAL SIDE/TOP COMBO-B499 .50X1X.375DIA |
| X1205 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Real Time Clock/Calendar |
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