參數(shù)資料
型號(hào): X1203
英文描述: 2-Wire RTC(Real Time Clock)/Calendar/Alarm(實(shí)時(shí)時(shí)鐘/日歷/警報(bào))
中文描述: 2線(xiàn)實(shí)時(shí)時(shí)鐘(實(shí)時(shí)時(shí)鐘)/日歷/鬧鐘(實(shí)時(shí)時(shí)鐘/日歷/警報(bào))
文件頁(yè)數(shù): 12/19頁(yè)
文件大小: 84K
代理商: X1203
X1203
12
Figure 11. Sequential Read Sequence
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to the CCR. Slave bits
1101 access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to 111.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 12.
After loading the entire Slave Address Byte from the
SDA bus, the device compares the device identifier and
device select bits with 1101111. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following the Slave Byte is a two byte CCR address.
The CCR address is either supplied by the master
device or obtained from an internal counter.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is, for a random read of the
Clock/Control Registers, the slave byte must be
1101111x in both places.
Figure 12. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Slave Address Byte
Byte 0
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
Data Byte
Byte 3
A6
A5
0
0
0
0
0
0
0
1
1
0
1
1
1
R/W
1
Device Identifier
0
High Order Word Address
Byte 1
-
X1203
Low Order Word Address
Byte 2
-
X1203
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