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參數(shù)資料
| 型號(hào)： | X1203 |
| 英文描述： | 2-Wire RTC(Real Time Clock)/Calendar/Alarm(實(shí)時(shí)時(shí)鐘/日歷/警報(bào)) |
| 中文描述： | 2線實(shí)時(shí)時(shí)鐘（實(shí)時(shí)時(shí)鐘）/日歷/鬧鐘（實(shí)時(shí)時(shí)鐘/日歷/警報(bào)） |
| 文件頁(yè)數(shù)： | 6/19頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | X1203 |
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X1203
6
CONTROL REGISTERS
Interrupt Control Bits (AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output. The interrupt output is enabled when either bit
is set to ‘1’. Two volatile bits (AL1 and AL0), associated
with these alarms, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the alarm interrupts are enabled. The AL1 and
AL0 bits are reset by the falling edge of the 8th clock
of a read of the register containing the bits.
In an alternative mode (called pulsed interrupt mode),
controlled by an interrupt mode (IM) bit, the alarm 0
setting provides an output pulse on IRQ each time the
alarm matches the RTC. In this case the AL0 bit is not
used. Alarm 1 works as before (i.e. the AL1 bit is set
when an alarm occurs), but it is necessary to poll the
status register to determine whether a match has
occurred. This read operation is necessary to reset the
AL1 flag.
Normal Mode (IM bit =0)
A match of the RTC and the contents of the alarm 0
registers automatically sets the AL0 bit. If the AL0E bit
is also set, the output IRQ signal goes active (LOW). If
the AL0E bit is not set, the AL0 bit is set, but the IRQ
signal remains unchanged.
A match of the RTC and the contents of the alarm 1
registers automatically sets the AL1 bit. If the AL1E bit
is also set, the output IRQ signal goes active (LOW). If
the AL1E bit is not set, the AL1 bit is set, but the IRQ
signal remains unchanged.
Reading the status register, containing the AL0 and
AL1 bits, resets the bits. The bits do not reset until the
falling edge of the 8th output clock of the status regis-
ter containing the Alarm bits. When the bits reset, the
output IRQ signal returns to the inactive state.
Pulsed Interrupt Mode (IM bit =1)
In this mode, the alarm interrupt enable bits (AL0E and
AL1E) are not used. Alarm 1 operates as before, so a
match of the RTC and Alarm 1 sets the AL1 bit. Since
the interrupt enable bits have no function, it is neces-
sary for the host processor to poll the AL1 bit to deter-
mine if an alarm has occurred.
Alarm 0 provides an output response. In this case,
when the RTC matches the Alarm 0 registers, the out-
put IRQ pulses one time. This pulse can be used to
control some outside circuit or event, without the need
for a local processor. The pulse is about 30ms in dura-
tion. All alarm 0 mask options are available, so this
becomes a very flexible long term repeat trigger.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/con-
trol register requires the following steps:
—Write a 02H to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
—Write a 06H to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
—Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write write
cycle, so the sequence must be repeated to again
initiate another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
—Writing all zeros to the status register resets both
the WEL and RWEL bits.
—A read operation occurring between any of the pre-
vious operations will not interrupt the register write
operation.
—The RWEL and WEL bits can be reset by writing a 0
to the Status Register.
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
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PDF描述 |
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| x1205(中文) | Real Time Clock/Calendar(實(shí)時(shí)時(shí)鐘/日期) |
| X1205V8 | Real Time Clock/Calendar |
| X1205V8I | Real Time Clock/Calendar |
| X1205 | Real Time Clock/Calendar |
| X1205S8 | Real Time Clock/Calendar |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| X1203S8 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:IC-SMD-RTC WITH EEPROM |
| X1203S8I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Real-Time Clock |
| X1203V8 | 制造商:Intersil Corporation 功能描述: |
| X-120-499 | 制造商:Brady Corporation 功能描述:VIAL SIDE/TOP COMBO-B499 .50X1X.375DIA |
| X1205 | 制造商:XICOR 制造商全稱(chēng):Xicor Inc. 功能描述:Real Time Clock/Calendar |
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