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參數(shù)資料
| 型號(hào)： | WM8148 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | TVS BIDIRECT 400W 5.0V SMA |
| 中文描述： | 12-bit/12MSPS防治荒漠化公約/獨(dú)聯(lián)體模擬前端/數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 7/43頁(yè) |
| 文件大小： | 491K |
| 代理商： | WM8148 |
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WM8148
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
7
INPUT VIDEO SAMPLING (EXTERNAL VSMP)
MCLK
VSMP
INPUT
VIDEO
t
PER
t
VSMPSU
t
VSMPH
t
VSU
t
VH
t
RSU
t
RH
Figure 1 Input Video Timing (External VSMP)
TEST CONDITIONS
AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70
°
C, MCLK = 48MHz unless
otherwise stated (AVDD denotes the voltage applied to all AVDD pins).
PARAMETER
MCLK period
(dependent on mode selected)
MCLK duty cycle
SYMBOL
t
PER
TEST CONDITIONS
MIN
20.8
TYP
MAX
UNITS
ns
45
55
%
VSMP set-up time
t
VSMPSU
2
ns
VSMP hold time
t
VSMPH
5
ns
Video level set-up time
t
VSU
10
ns
Video level hold time
t
VH
10
ns
Reset level set-up time
t
RSU
10
ns
Reset level hold time
t
RH
10
ns
Notes:
1.
t
VSU
and t
RSU
denote the set-up time required from when the input video signal has settled.
The reset sample point may be relative to either the rising or the falling edge of MCLK, depending on the setting of
control bits RESREF[3:0].
Parameters are measured at 50% of the rising/falling edge.
2.
3.
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