參數(shù)資料
型號: WM8148
廠商: Wolfson Microelectronics
英文描述: TVS BIDIRECT 400W 5.0V SMA
中文描述: 12-bit/12MSPS防治荒漠化公約/獨聯(lián)體模擬前端/數(shù)字轉(zhuǎn)換器
文件頁數(shù): 17/43頁
文件大?。?/td> 491K
代理商: WM8148
WM8148
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
17
RESET LEVEL CLAMPING (RLC)
If the sensor output voltage is within the input range of the WM8148, the sensor may be d.c. coupled
into the WM8148 either directly or via a buffer. If the output from the sensor is outside the input range
of the WM8148, the signal has to be connected via a capacitor, C
IN
, and the d.c. bias conditions must
be defined on the WM8148 side of the capacitor (at RINP).
Setting of the d.c. bias conditions is best performed by Reset-Level Clamping, activated by pin RLC.
Reset-Level Clamping is compatible with both CDS and non-CDS operating modes. A typical
configuration is shown in Figure 16.
TIMING CONTROL
R
S
S/H
4-BIT
RLC DAC
CL
+
+
-
TO OFFSET DAC
RLC
CDS
FROM CONTROL
INTERFACE
S/H
V
S
FROM CONTROL
INTERFACE
MCLK
VSMP
RLC
INPUT SAMPLING
BLOCK FOR RED
CHANNEL
MODE[0]
C
IN
RINP
VRLC
2
1
EXTERNAL VRLC
Figure 16 Reset-Level Clamping Circuitry
When the clamp pulse, CL, is active, the voltage on the WM8148 side of C
IN
, at RINP, will be forced
equal to the VRLC voltage, V
VRLC
, by switch 1. When the CL pulse turns off, the RINP voltage will
initially remain at V
VRLC
, but any subsequent variation in sensor voltage appearing at the sensor side
of C
IN
will couple through C
IN
to RINP. Switch 2 determines whether the R
S
level is taken from the
incoming signal (CDS operation) or the VRLC pin (non-CDS operation).
Figure 17 demonstrates the case of a typical CCD waveform, with CL applied during the reset period.
MCLK
VSMP
RLC
CL
Input Video
1
X
X
X
X
0
0
X
r,g,b
r,g,b
r,g,b
RLC on this pixel
No RLC on this pixel
Programmable Delay
Figure 17 Relationship of RLC pin, MCLK and VSMP to Internal Clamp Pulse, CL
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal
CL pulse on the next reset level. The position and duration of CL is adjustable by control bits
RESREF[3:0] and SMALL.
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