參數(shù)資料
型號(hào)： WM8148
廠(chǎng)商： Wolfson Microelectronics
英文描述： TVS BIDIRECT 400W 5.0V SMA
中文描述： 12-bit/12MSPS防治荒漠化公約/獨(dú)聯(lián)體模擬前端/數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 16/43頁(yè)
文件大小： 491K
代理商： WM8148
WM8148
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
16
INPUT SAMPLING MODES
To suit different sensors and applications, the WM8148 can sample one, two, or three channels
simultaneously, at the rate of the VSMP clock. In each case there are two possible ratios of VSMP
frequency to the MCLK master clock frequency, and a choice of whether to use CDS. Table 1
summarises the options available, including the respective maximum sample rates. The mode of
operation is set by the Control Register bits MODE[3:0] as shown. Note MODE[0] defines whether or
not CDS is activated.
MAX
SAMPLE
RATE PER
CHANNEL
(VSMP)
MSPS
MCLK/VSMP
FREQUENCY
RATIO
MAX MCLK
FREQENCY
MAX
OUTPUT
RATE
MODE
NUMBER
(MODE[3:0])
MHz
MSPS
CDS
NON-
CDS
1
Three-channel
(8-phase)
Three-channel
(12-phase)
Two-channel
(6-phase)
Two-channel
(8-phase)
One-channel
CDS
One-channel
non-CDS
4
8
32
12
0
4
12
48
12
8
9
5.33
6
32
10.66
4
5
6
8
48
12
12
13
6.66
6
40
6.66
2
N/A
10
4
40
10
N/A
3
Table 1 Modes of Operation
If an external VSMP signal is not available, the WM8148 can be configured to output a
synchronisation pulse to the system by setting control bit FREE. The internally generated signal is
presented on the VSMP and/or SDO pins depending on the settings of the control bits VSMPOP and
SDO[1:0].
CORRELATED DOUBLE SAMPLING (CDS)
The input signal can be sampled in two ways: Correlated Double Sampling (CDS), or non-CDS.
CDS operation is summarised in Figure 15. The video signal processed is the difference between the
voltage applied at the RINP input when R
S
turns off and the voltage at the RINP input when V
S
turns
off, i.e. the difference between reset and video levels from the same pixel of the input signal. This
method of sampling is recommended as it removes common-mode noise.
R
S
V
S
V
RS
V
VS
Figure 15 CDS Reset and Video Level Sampling
In non-CDS modes, R
S
and V
S
occur simultaneously. V
S
samples the video signal, while R
S
samples
the reference level applied to the VRLC pin. The video signal processed is the difference between
these samples (V
RS
-V
VS
). The voltage (V
VRLC
), on pin VRLC, may be driven externally or internally by
the RLC DAC. In these modes d.c. variations of the input signal are not rejected.
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