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參數(shù)資料
| 型號： | WM8148 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | TVS BIDIRECT 400W 5.0V SMA |
| 中文描述： | 12-bit/12MSPS防治荒漠化公約/獨聯(lián)體模擬前端/數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 491K |
| 代理商： | WM8148 |
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WM8148
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
15
DEVICE DESCRIPTION
INTRODUCTION
The WM8148 samples up to three analogue inputs simultaneously, conditions these signals and
converts each resulting analogue signal to a 12-bit digital word.
A block diagram is shown on page 1. Each of the three input channels consists of an Input Sampling
block (CDS/RLC), an 8-bit programmable Offset DAC, and a 6-bit Programmable Gain Amplifier
(PGA). The outputs from the three channels are multiplexed into a 12-bit ADC. The digital output from
the ADC is presented on a 12-bit wide bi-directional bus.
A high-speed (up to 48MHz) master clock, MCLK, and a per-pixel synchronisation pulse, VSMP, drive
a shared Timing Control block to generate input sampling signals and other internal clocks.
Alternatively the device can operate from MCLK only, outputting VSMP synchronisation pulses to the
rest of the system.
An internal reference provides buffered voltages VRT, VRB and VRX. A 4-bit DAC (RLC DAC)
provides a programmable buffered voltage at pin VRLC for use as an input signal reference level or
an input clamp voltage.
The operation of the device is controlled by internal control registers, which can be read from and
written to via a Digital Management Interface (DMI) in either serial or parallel mode.
INPUT SAMPLING
Figure 14 shows the configuration of the Input Sampling Block for the red channel. (The green and
blue channels are the same.)
TIMING CONTROL
R
S
RINP
VRLC
S/H
4-BIT
RLC DAC
CL
+
+
-
To Offset DAC
RLC
CDS
From Control Interface
S/H
V
S
From Control Interface
MCLK
VSMP
RLC
INPUT SAMPLING
BLOCK FOR RED
CHANNEL
MODE[0]
Figure 14 Input Sampling Block – Configuration for Red Channel
This block contains switches to perform Reset Level Clamping (RLC) and Correlated Double
Sampling (CDS). Sample/Hold blocks sample the video and reset/reference levels of the input
waveform, and pass the difference signal on to the rest of the channel. Internal clocks V
S
and R
S
define the timing of the sampling of the video signal and the reset/reference level respectively. When
enabled by control input pin RLC, internal signal CL clamps the input pin RINP to the voltage on pin
VRLC, which is driven either externally or from the 4-bit RLC DAC.
The detailed timing of the internal clock signals CL, V
S
, and R
S,
with respect to VSMP and MCLK, is
controlled by the Timing Control block as programmed via the Digital Management Interface (DMI).
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