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參數(shù)資料
| 型號(hào)： | WEDPS512K32-35BC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 35 ns, PBGA143 |
| 封裝： | 16 X 18 MM, PLASTIC, BGA-143 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 202K |
| 代理商： | WEDPS512K32-35BC |
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPS512K32-XBX
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
FIG. 4 AC TEST CIRCUIT
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
W.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
Parameter
Symbol
-12
-15
-17
-20
-25
-35
-45
-55
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max Min
Max
Min
Max Min
Max
Read Cycle Time
tRC
12
15
17
20
25
35
45
55
ns
Address Access Time
tAA
12
15
17
20
25
35
45
55
ns
Output Hold from Address Change
tOH
00
0
ns
Chip Select Access Time
tACS
12
15
17
20
25
35
45
55
ns
Output Enable to Output Valid
tOE
7
8
9
10
12
25
ns
Chip Select to Output in Low Z
tCLZ1
12
22
24
4
ns
Output Enable to Output in Low Z
tOLZ1
00
0
ns
Chip Disable to Output in High Z
tCHZ1
7
121212
1215
20
ns
Output Disable to Output in High Z
tOHZ1
7
121212
1215
20
ns
Parameter
Symbol
-12
-15
-17
-20
-25
-35
-45
-55
Units
Read Cycle
Min
Max
Min
Max
Min
Max
Min
Max Min
Max
Min
Max Min
Max
Write Cycle Time
tWC
12
15
17
20
25
35
45
55
ns
Chip Select to End of Write
tCW
10
13
15
17
25
35
50
ns
Address Valid to End of Write
tAW
10
13
15
17
25
35
50
ns
Data Valid to End of Write
tDW
8
10
1112
1320
25
ns
Write Pulse Width
tWP
10
13
15
17
25
35
40
ns
Address Setup Time
tAS
02
22
2
ns
Address Hold Time
tAH
00
5
ns
Output Active from End of Write
tOW1
22
23
44
5
ns
Write Enable to Output in High Z
tWHZ1
7
8
9
11
13
15
20
ns
Data Hold Time
tDH
00
0
1. This parameter is guaranteed by design but not tested.
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