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參數(shù)資料
| 型號(hào)： | WEDPN8M72VR-66I |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 208K |
| 代理商： | WEDPN8M72VR-66I |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN8M72VR-XBX
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge
n, and the latency
is
m clocks, the data will be available by clock edge n+m. The I/
Os will start driving as a result of the clock edge one cycle earlier
(
n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge
n + m. For example, assuming
that the clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the latency is
programmed to two clocks, the I/Os will start driving after T1 and
the data will be valid by T2. Table 2 below indicates the operating
frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7and M8 to
zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length
applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because
TABLE 2 - CAS LATENCY
FIG. 4
CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CAS
SPEED
LATENCY = 2
LATENCY = 3
-100
≤ 66
≤ 100
-66
≤ 50
≤ 66
CLK
I/O
T2
T1
T3
T0
CAS Latency = 3
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
I/O
T2
T1
T3
T0
CAS Latency = 2
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
unknown operation or incompatibility with future versions may
result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to
both READ and WRITE bursts; when M9 = 1, the programmed burst
length applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
COMMANDS
The Truth Table provides a quick reference of available com-
mands. This is followed by a written description of each com-
mand. Three additional Truth Tables appear following the Opera-
tion section; these tables provide current state/next state infor-
mation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPN8M72VR-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Registered SDRAM MCP |
| WEDPN8M72V-XB2X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
| WEDPNF8M721V-1010BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1010BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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