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參數(shù)資料
| 型號： | WEDPN8M72VR-66I |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 208K |
| 代理商： | WEDPN8M72VR-66I |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN8M72VR-XBX
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command which
is then followed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0 and BA1 select the
bank, A0-11 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register definition, command descriptions and de-
vice operation.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified may
result in undefined operation. Once power is applied to VDD and
VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for
the clock pin), the SDRAM requires a 100
s delay prior to issuing
any command other than a COMMAND INHIBIT or a NOP. Starting
at some point during this 100
s period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP
commands should be applied.
Once the 100
s delay has been satisfied with at least one COM-
MAND INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must be precharged,
thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be per-
formed. After the AUTO REFRESH cycles are complete, the SDRAM
is ready for Mode Register programming. Because the Mode
Register will power up in an unknown state, it should be loaded
prior to applying any operational command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of opera-
tion of the SDRAM. This definition includes the selec-tion of a
burst length, a burst type, a CAS latency, an operating mode and
a write burst mode, as shown in Figure 3. The Mode Register is
programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the
device loses power.
Mode register bits M0-M2 specify the burst length, M3 specifies
the type of burst (sequential or interleaved), M4-M6 specify the
CAS latency, M7 and M8 specify the operating mode, M9 speci-
fies the WRITE burst mode, and M10 and M11 are reserved for
future use.
The Mode Register must be loaded when all banks are idle, and
the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will
result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented, with
the burst length being programmable, as shown in Figure 3. The
burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst
is available for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst will
wrap within the block if a boundary is reached. The block is
uniquely selected by A1-8 when the burst length is set to two; by
A2-8 when the burst length is set to four; and by A3-8 when the
burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location within
the block. Full-page bursts wrap within the page if the boundary
is reached.
Burst Type
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type and
is selected via bit M3.
The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown
in Table 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPN8M72VR-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Registered SDRAM MCP |
| WEDPN8M72V-XB2X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
| WEDPNF8M721V-1010BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1010BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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