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參數(shù)資料
| 型號： | WEDPN8M72VR-66I |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 208K |
| 代理商： | WEDPN8M72VR-66I |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN8M72VR-XBX
WRITE
The WRITE command is used to initiate a burst write access to an
active row. The value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-8 selects the starting column
location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for subsequent
accesses. Input data appearing on the I/Os is written to the memory
array subject to the DQM input logic level appearing coincident with
the data. If a given DQM signal is registered LOW, the corresponding
data will be written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in
a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row access a specified time (tRP) after
the PRECHARGE command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has
been precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same indi-
vidual-bank PRECHARGE function described above, without re-
quiring an explicit command. This is accomplished by using A10 to
enable AUTO PRECHARGE in conjunction with a specific READ or
WRITE command. A precharge of the bank/row that is addressed
with the READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in the full-
page burst mode, where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated at the
earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge time (tRP) is
completed. This is determined as if an explicit PRECHARGE com-
mand was issued at the earliest possible time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-
length or full-page bursts. The most recently registered READ or
WRITE command prior to the BURST TERMINATE command will be
truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM
and is analagous to CAS-BEFORE-RAS (CBR) REFRESH in conven-
tional DRAMs. This command is nonpersistent, so it must be
issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This
makes the address bits “Don’t Care” during an AUTO REFRESH
command. Each 128Mb SDRAM requires 4,096 AUTO REFRESH
cycles every refresh period (tREF). Providing a distributed AUTO RE-
FRESH command will meet the refresh requirement and ensure that
each row is refreshed. Alternatively, 4,096 AUTO REFRESH com-
mands can be issued in a burst at the minimum cycle rate (tRC), once
every refresh period (tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data in the
SDRAM, even if the rest of the system is powered down. When in
the self refresh mode, the SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which must
remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own
internal clocking, causing it to perform its own AUTO REFRESH
cycles. The SDRAM must remain in self refresh mode for a
minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin)
prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR,
because time is required for the completion of any internal refresh
in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands
must be issued as both SELF REFRESH and AUTO REFRESH utilize
the row refresh counter.
* Self refresh available in commercial and industrial tempera-
tures only.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPN8M72VR-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Registered SDRAM MCP |
| WEDPN8M72V-XB2X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
| WEDPNF8M721V-1010BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1010BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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