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參數(shù)資料
| 型號： | WED9LAPC2C16P8BI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, PBGA153 |
| 封裝： | 14 X 22 MM, BGA-153 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 693K |
| 代理商： | WED9LAPC2C16P8BI |
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2B16P8BC
November 2001
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIGURE 5 – SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
tRC
tRCD
Note 1
Ra
Ca0
Cb0
Rb
Ra
tRAC
Note 3
tSAC
tOH
tSHZ Note 4
tRDL
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Notes:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is
available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED9LAPC2C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC2C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LC6416V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
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