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參數(shù)資料
| 型號(hào)： | WED2DL36514V25BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 2.5 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 266K |
| 代理商： | WED2DL36514V25BC |
10
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL36513V
WED2DL36513AV
FIG. 5 READ/WRITE TIMING DIAGRAM
ADSP
ADSC
ADDRESS
BWx
(NOTE 4)
CE
(NOTE 2)
tADSS
tADSH
ADV
OE
CLOCK
A2
tAS tAH
Q
tKH
tKL
tKC
tOELZ
Q(A4+2)
Q(A4)
Q(A1)
Q(A4+1)
Q(A4+3)
tKQLZ
tKQ
tOEHZ
Back-to-Back READs
(NOTE5)
SINGLE WRITE
Back-to-Back
WRITEs
BURST READ
Q(A2)
(NOTE 3)
A5
A6
DON’T CARE
UNDEFINED
tCSS tCSH
tWS tWH
(NOTE 1)
HIGH-Z
D
HIGH-Z
A1
A3
A4
(NOTE 4)
D(A3)
D(A5)
D(A6)
tDS
tDH
NOTES:
1. Q (A4) refers to output from address A4. Q (A4+1) refers to output from the next internal burst address following A4.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and
CE2 is LOW.
3. The data bus Q remains in High-Z following a WRITE cycle unless ADSP, ADSC or ADV cycle is performed.
4. GW is HIGH.
5. Back-to-back READs may be controlled by either ADSP or ADSC.
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