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參數(shù)資料
| 型號(hào)： | WED2DL32512V38BC |
| 元件分類： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 3.8 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 143K |
| 代理商： | WED2DL32512V38BC |
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL32512V
INTERLEAVED BURST TABLE (MODE = NC OR HIGH)
First Address
Second Address
Third Address
Fourth Address
External
Internal
X...X00
X...X01
X...X10
X...X11
X...X01
X....X00
X...X11
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
INTERLEAVED BURST TABLE (MODE = LOW)
First Address
Second Address
Third Address
Fourth Address
External
Internal
X...X00
X...X01
X...X10
X...X11
X...X01
X....X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
TRUTH TABLE
Function
Address
CE
ZZ
ADSC
WRITE
OE
CLK
DQ
Used
Deselected Cycle, Power-Down
None
H
L
X
L-H
High-Z
Deselected Cycle, Power-Down
None
L
X
L-H
High-Z
SNOOZE MODE, Power-Down
None
X
H
X
High-Z
WRITE Cycle, Begin Burst
External
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
X
L
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
L
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
L
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
L
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
L
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
L
H
L
X
L-H
D
NOTES:
1. X means “Don’t Care.” —— means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s. BWc enables WRITEs to DQc’s. BWd enables WRITEs to DQd’s.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED2DL32512V38BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SYNC SRAM|512KX32|CMOS|BGA|119PIN|PLASTIC |
| WED2DL32512V40BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SYNC SRAM|512KX32|CMOS|BGA|119PIN|PLASTIC |
| WED2DL32512V40BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx32 Synchronous Pipeline Burst SRAM |
| WED2DL32512V-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SSRAM MCP |
| WED2DL32512V-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TMS320C6202. TMS320C6203. TMS320C6204. TMS320C6 Families |
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