參數(shù)資料
型號: WE512K8300CI
元件分類: PROM
英文描述: 512K X 8 EEPROM 5V MODULE, 300 ns, CDIP32
封裝: SINGLE CAVITY, CERAMIC, DIP-32
文件頁數(shù): 9/13頁
文件大?。?/td> 133K
代理商: WE512K8300CI
White Microelectronics Phoenix, AZ (602) 437-1520
10
EEPROM
MODULES
5
WE512K8, WE256K8, WE128K8-XCX
Figure 5 shows Read cycle waveforms. A read cycle begins
with selection address, chip select and output enable. Chip
select is accomplished by placing the CS line low. Output
enable is done by placing the OE line low. The memory places
the selected data byte on I/O0 through I/O7 after the access
time. The output of the memory is placed in a high impedance
state shortly after either the OE line or CS line is returned to a
high level.
READ
AC READ CHARACTERISTICS (SEE FIGURE 5)
FOR WE512K8-XCX
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
Parameter
Symbol
-150
-200
-250
-300
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
150
200
250
300
ns
Address Access Time
tACC
150
200
250
300
ns
Chip Select Access Time
tACS
150
200
250
300
ns
Output Hold from Address Change, OE or CS
tOH
00
ns
Output Enable to Output Valid
tOE
85
100
125
ns
Chip Select or Output Enable to High Z Output
tDF
70
ns
FOR WE256K8-XCX AND WE128K8-XCX
Parameter
Symbol
-150
-200
Unit
Min
Max
Min
Max
Read Cycle Time
tRC
150
200
ns
Address Access Time
tACC
150
200
ns
Chip Select Access Time
tACS
150
200
ns
Output Hold from Address Change, OE or CS
tOH
10
ns
Output Enable to Output Valid
tOE
85
100
ns
Chip Select or Output Enable to High Z Output
tDF
70
ns
FIG. 5
READ WAVEFORMS
t
ADDRESS
CS
OE
OUTPUT
OH
tDF
t ACC
t RC
t OE
tACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
NOTE:
OE may be delayed up to tACS-
tOE after the falling edge of CS
without impact on tOE or by tACC-
tOE after an address change
without impact on tACC.
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