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| 型號(hào)： | WC32P020-XXM |
| 英文描述： | 16 32-Bit General-Purpose Data and Address Registers |
| 中文描述： | 16 32位通用數(shù)據(jù)和地址寄存器 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大小： | 488K |
| 代理商： | WC32P020-XXM |
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8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P020-XXM
December 2002
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
AC ELECTRICAL SPECIFICATIONS – READ AND WRITE CYCLES
V
CC
= 5.0 V
DC
± 5%, GND = 0 V
DC
, -55°C ≤ T
A
≤ +125°C
Characteristic
Clock high to Address, FC, Size, RMC# Valid
Clock High to ECS#, OCS# Asserted
Clock High to Address, Data, FC, Size, RMC#, High Impedance
Clock high to Address, FC, Size, RMC# Invalid
Clock Low to AS#, DS# Asserted
AS# to DS# Assertion (Read) (Skew)
AS# Asserted to DS# Asserted (Write)
ECS# Width Asserted
OCS# Width Asserted
ECS#, OCS# width Negated
Address, FC, Size, RMC#, Valid to AS# (and DS# Asserted Read)
Clock Low to AS#, DS# Negated
Clock Low to ECS#, OCS# Negated
AS#, DS# Negated to Address, FC, Size, RMC# Invalid
AS# (and DS# Read) Width Asserted
DS# Width Asserted Write
AS#, DS# Width Negated
DS# Negated to AS# Asserted
Clock High to AS#, DS#, R/W# Invalid, High Impedance
AS#, DS# Negated to R/W# Invalid
Clock High to R/W# High
Clock High to R/W# Low
R/W# High to AS# Asserted
R/W# Low to DS# Asserted (Write)
Clock High to Data Out Valid
DS# Negated to Data Out Invalid
DS# Negated to DBEN# Negated (Write)
Data Out Valid to DS# Asserted (Write)
Data-In Valid to Clock Low (Data Setup)
Late BERR#/HALT# Asserted to Clock Low Setup Time
AS#, DS# Negated to DSACKx#, BERR#, HALT#, AVEC# Negated
DS# Negated to Data-In Invalid (Data-In Hold Time)
DS# Negated to Data-In (High Impedance)
DSACKx# Asserted to Data-In Valid
DSACKx# Asserted to DSACKx# Valid (DSACK# Asserted Skew)
RESET# Input Transition Time
Clock Low to BG# Asserted
Clock Low to BG# Negated
BR# Asserted to BG# Asserted (RMC# Not Asserted)
BGACK# Asserted to BG# Negated
Specification
6
6A
7
8
9
9A (1)
9B (11)
10
10
10B (7)
11
12
12A
13
14
14A
15
15A (8)
16
17
18
20
21
22
23
25
25A (9)
26
27
27A
28
29
29A
31 (2)
31A (3)
32
33
34
35
37
16.67 MHz
Min
0
0
0
0
1
-15
37
20
20
15
15
0
0
15
100
40
40
35
—
15
0
0
15
75
—
15
15
15
5
20
0
0
—
—
—
—
0
0
1.5
1.5
20 MHz
Min
0
0
0
0
1
-10
32
15
15
10
10
0
0
10
85
38
38
30
—
10
0
0
10
60
—
10
10
10
5
15
0
0
—
—
—
—
0
0
1.5
1.5
25 MHz
Min
0
0
0
0
1
-10
27
15
15
5
6
0
0
10
70
30
30
25
—
10
0
0
5
50
—
5
5
5
5
10
0
0
—
—
—
—
0
0
1.5
1.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clks
ns
ns
Clks
Clks
Max
30
20
60
—
30
15
—
—
—
—
—
30
30
—
—
—
—
—
60
—
30
30
—
—
30
—
—
—
—
—
80
—
60
50
15
1.5
30
30
3.5
3.5
Max
25
15
50
—
25
10
—
—
—
—
—
25
25
—
—
—
—
—
50
—
25
25
—
—
25
—
—
—
—
—
65
—
50
43
10
1.5
25
25
3.5
3.5
Max
25
12
40
—
18
10
—
—
—
—
—
15
15
—
—
—
—
—
40
—
20
20
—
—
25
—
—
—
—
—
50
—
40
32
10
1.5
20
20
3.5
3.5
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