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參數(shù)資料
| 型號(hào)： | WC32P020-XXM |
| 英文描述： | 16 32-Bit General-Purpose Data and Address Registers |
| 中文描述： | 16 32位通用數(shù)據(jù)和地址寄存器 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 488K |
| 代理商： | WC32P020-XXM |
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P020-XXM
December 2002
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
ADDRESSING MODES
Addressing
Register Direct
Data Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
Syntax
Dn
An
(An)
(An) +
- (An)
(d16,An)
(d8,An,Xn)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d16,PC)
(d8,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
(
xxx).W
(xxx).L
#(data)
NOTES:
d8, d16 = A twos-complement or sign-extended displacement; added as part of the
effective address calculation; size is 8 (d8) or 16 (d16) bits; when omitted,
assemblers use a value of zero.
Xn = Address or data register used as an index register; form is Xn.SIZE*SCALE,
where SIZE is.W or .L (indicates index register size) and SCALE is 1, 2, 4,
or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is
optional.
bd = A twos-complement base displacement; when present, size can be 16 or 32
bits.
od = 0uter displacement, added as part of effective address calculation after any
memory indirection, use is optional with a size of 16 or 32 bits.
PC = Program Counter
(data) = Immediate value of 8, 16, or 32 bits
( ) = Effective Address
[ ] = Use as indirect access to long-word address.
Dn = Data Register, DO-D7
An = Address Register, AO-A7
Mnemonic
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CALLM
CAS
CAS2
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EXG
EXT, EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE CCR
MOVE SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
Description
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Call Module
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and Lower Bounds
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive OR
Logical Exclusive OR Immediate
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move Condition Code Register
Move Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiple
INSTRUCTION SET
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
Arithmetic Shift Left and Right
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR
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