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參數(shù)資料
| 型號： | WC32P020-XXM |
| 英文描述： | 16 32-Bit General-Purpose Data and Address Registers |
| 中文描述： | 16 32位通用數(shù)據(jù)和地址寄存器 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 488K |
| 代理商： | WC32P020-XXM |
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WC32P020-XXM
December 2002
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
INSTRUCTION SET (cont'd)
Description
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive OR
Logical Inclusive OR Immediate
Logical Inclusive OR Immediate to Condition Codes
Logical Inclusive OR Immediate to Status Register
Pack BCD
Push Effective Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return from Module
Return and Restore Codes
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
Mnemonic
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
ORI CCR
ORI SR
PACK
PEA
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTM
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
COPROCESSOR INSTRUCTIONS
Mnemonic
Description
cpBcc
Branch Conditionally
cpDBcc
Test Coprocessor Condition, Decrement and Branch
cpGEN
Coprocessor General Instruction
Mnemonic
cpRESTORE
cpSAVE
cpScc
cpTRAPcc
Description
Restore Internal State of Coprocessor
Save Internal State of Coprocessor
Set Conditionally
Trap Conditionally
FIGURE 4 – FUNCTIONAL SIGNAL GROUPS
FC0-FC2
A0-A31
D0-D31
SIZ0
SIZ1
RESET#
HALT#
BERR#
CLK
Vcc (10)
GND (13)
IPRIORITY
CDIS#
IPEND#
AVEC#
BR#
BG#
BGACK#
ECS#
OCS#
RMC#
AS#
DS#
R/W#
DBEN#
DSACK0#
DSACK1#
ASYNCHRONOUS
BUS CONTROL
INTERRUPT
CONTROL
IPL0#-IPL2#
BUS ARBITRATION
BUS EXCEPTION
TRANSIZE
CACHE
CONTROL
FUCODES
ADDRBUS
BUS
SIGNAL DESCRIPTION
The V
CC
and GND pins are separated into four groups
to provide individual power supply connections for the
address bus buffers, data bus buffers, and all other buffers
and internal logic. See FIGURE 4.
Group
Address Bus
Data Bus
Logic
Clock
V
CC
A9, D3
M8, N8, N13
D1, D2, E3, G11, G13
—
GND
A10, B9, C3, F12
L7, L11, N7, K3
G12, H13, J3, K1
B1
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