參數(shù)資料
型號： W942508BH
英文描述： DRAM
中文描述： 內(nèi)存
文件頁數(shù)： 9/45頁
文件大?。?/td> 1601K
代理商： W942508BH
W942508BH
Publication Release Date: March 19, 2002
- 9 -
Revision A1
11. DC CHARACTERISTICS
MAX.
-7
SYM.
PARAMETER
-75
UNIT
NOTES
I
DD0
OPERATING CURRENT: One Bank Active-Precharge; t
RC
= t
RC
min; t
CK
=
t
CK
min; DQ, DM and DQS inputs changing twice per clock cycle; Address
and control inputs changing once per clock cycle
OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2;
t
RC
= t
RC
min; CL = 2.5; t
CK
= t
CK
min; I
OUT
= 0 mA; Address and control
inputs changing once per clock cycle.
PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle;
Power down mode; CKE < V
IL
max; t
CK
= t
CK
min; Vin = V
REF
for DQ, DQS
and DM
110
110
7
I
DD1
110
110
7, 9
I
DD2P
2
2
I
DD2F
IDLE FLOATING STANDBY CURRENT:
CS
> V
IH
min; All Banks Idle;
CKE > V
IH
min; Address and other control inputs changing once per clock
cycle; Vin = Vref for DQ, DQS and DM
45
40
7
I
DD2N
IDLE STANDBY CURRENT:
CS
> V
IH
min; All Banks Idle; CKE > V
IH
min; t
CK
= t
CK
min; Address and other control inputs changing once per
clock cycle; Vin > V
IH
min or Vin < V
IL
max for DQ, DQS and DM
45
40
7
I
DD2Q
IDLE QUIET STANDBY CURRENT:
CS
> V
IH
min; All Banks Idle; CKE >
V
IH
min; t
CK
= t
CK
min; Address and other control inputs stable; Vin > V
REF
for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power
down mode; CKE < V
IL
max; t
CK
= t
CK
min
40
35
mA
7
I
DD3P
20
20
I
DD3N
ACTIVE STANDBY CURRENT:
CS
> V
IH
min; CKE > V
IH
min; One Bank
Active-Precharge; t
RC
= t
RAS
max; t
CK
= t
CK
min; DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle; CL=2.5;
t
CK
= t
CK
min; I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle; CL =
2.5; t
CK
= t
CK
min; DQ, DM and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT: t
RC
= t
RFC
min
SELF REFRESH CURRENT: CKE < 0.2V
RANDOM READ CURRENT: 4 Banks Active Read with activate every
20ns, Auto-Precharge Read every 20 nS; Burst = 4; t
RCD
= 3; I
OUT
= 0mA;
DQ, DM and DQS inputs changing twice per clock cycle; Address
changing once per clock cycle
70
65
7
I
DD4R
165
155
7, 9
I
DD4W
165
155
7
I
DD5
I
DD6
190
3
190
3
7
I
DD7
270
270
CK
CK
DQS
RANDOM READ CURRENT Timing
t
RCD
t
RC
t
CK = 10ns
(
I
DD7)
Row d
Row c
Col c
Row e
Row e
Col e
ADDRESS
Row d
Col d
Row f
Row q
Col f
READ
AP
ACT
READ
AP
COMMAND
READ
AP
ACT
ACT
READ
AP
ACT
DQ
Qa
Qb
Qb
Qb
Qb
Qc
Qc
Qc
Qc
Qd
Qd
Qd
Qd
Qe
Qe
Qa
Row h
ACT
Bank 0
Bank 1
Bank 2
Bank 3
Bank 2
Bank 0
Bank 1
Bank 3
Bank 0
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