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參數資料
| 型號： | W942508BH |
| 英文描述： | DRAM |
| 中文描述： | 內存 |
| 文件頁數： | 25/45頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | W942508BH |
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W942508BH
Publication Release Date: March 19, 2002
- 25 -
Revision A1
Address Sequence of Sequential Mode
A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as the following.
Addressing Sequence of Sequential Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
n
2 words (address bits is A0)
Data 1
n + 1
not carried from A0 to A1
Data 2
n + 2
4 words (address bit A0, A1)
Data 3
n + 3
Not carried from A1 to A2
Data 4
n + 4
Data 5
n + 5
8 words (address bits A2, A1 and A0)
Data 6
n + 6
Not carried from A2 to A3
Data 7
n + 7
Addressing Sequence of Interleave Mode
A Column access is started from the inputted column address and is performed by
interleaving the address bits in the sequence shown as the following.
Address Sequence for Interleave Mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
4 words
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
8 words
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
相關PDF資料 |
PDF描述 |
|---|---|
| W942516BH | DRAM |
| W9451GBDA-6 | SDRAM|DDR|64MX64|CMOS|DIMM|184PIN|PLASTIC |
| W981204AH-75 | x4 SDRAM |
| W981204AH-8H | x4 SDRAM |
| W982504AH-7 | x4 SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W942508CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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