參數(shù)資料
型號(hào)： W89C880F
英文描述： LAN Hub Controller
中文描述： 局域網(wǎng)集線器控制器
文件頁(yè)數(shù)： 61/72頁(yè)
文件大小： 731K
代理商： W89C880F
W89C840F
Publication Release Date:April 1997
Revision A1
- 61 -
T01, Transmit Descriptor 1
The T01 is used to describe the Transmit Control for the current frame transmission
The transmit DMA state machine will fetch the first descriptor of the current frame , at first, to
decide the transmission control configuration for the current frame. The transmit DMA state machine will
also fetch each descriptor before read the transmitted data from the data buffer in the host memory.
Bit
Symbol
Description
31
FINT
Frame Interupt.
The W89C840F will set the Transmit Interrupt bit(bit 0 of C14/CISR) after the
current frame was transmitted if the FINT is previously set by the driver
program. This bit is valid only when the current descriptor is the first descriptor
of the current frame (TFD set).
30
TLD
Last Descriptor.
When set, it indicates that this is the last descriptor of the current frame. The
TLD is valid on each descriptor.
29
TFD
First Descriptor.
When set, it indicates that this is the first descriptor of the current frame. The
TFD is valid on each descriptor.
When both TFD and TLD are high, it means that the current t
ransm tted
frame
is described by a single descriptor.
When both TRFD and TLD are low, it means that the current descriptor is
neither the first descriptor nor the last descriptor of the current frame.
When TLD is high and TFD is low, it means the current descriptor is the last
descriptor.
When TLD is low and TFD is high, it means the current descriptor is the first
descriptor.
26
ICRC
Inhibit CRC:
The W89C840F will inhibit CRC appending after the end of transmitted frame
when the ICRC is set by the driver program. Otherwise, the W89C840F appends
CRC after the end of transmitted frame when ICRC is reset.
This bit is valid only when First Descriptor bit (T01[29]) is set.
25
TLAST
Last Descriptor of the Ring.
When set, it indicates the current descriptor is the last one of the descriptor ring.
This bit preempts bit 24 (TLINK). It means that the next descriptor pointer of the
transmit DMA state machine will automatically jump to the first descriptor
pointed by register C10/CTDLA even the TLINK is set to high and the T03
points to an address other than the one specified by the C10/CTDLA. The
TLAST is valid on each decsriptor.
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