
W89C840F
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5
R/W
TFUE
Transmit FIFO Underflow Enable.
The Transmit FIFO Underflow Interrupt will be enabled if both
AIE(bit 15) and TFUE are set to high, otherwise, the Transmit
FIFO Underflow Interrupt will be disabled. The hardware interrupt
will be asserted if all of the bit AIE in C1C/CIMR, the bit TFUE in
C1C/CIMR and the bit IUF in C14/CISR are set to high.
4
R/W
RERRE
Receive Error Enable.
The Receive Error Interrupt will be enabled if both AIE(bit 15) and
RERRE are set to high, otherwise, the Receive Error Interrupt will
be disabled. The hardware interrupt will be asserted if all of the bit
AIE in C1C/CIMR, the bit RERRE in C1C/CIMR and the bit RERR
in C14/CISR are set to high.
3
R/W
REIE
Receive Early Interrupt Enable.
The Receive Early Interrupt will be enabled if both AIE(bit 15) and
REIE are set to high, otherwise, the Receive Early Interrupt will be
disabled. The hardware interrupt will be asserted if all of the bit
AIE in C1C/CIMR, the bit REIE in C1C/CIMR and the bit REI in
C14/CISR are set to high.
2
R/W
TBUE
Transmit Buffer Unavailable Enable.
The Transmit Buffer Unavailable Interrupt will be enabled if both
NIE(bit 16) and TBUE are set to high, otherwise, the Transmit
Buffer Unavailable Interrupt will be disabled. The hardware
interrupt will be asserted if all of the bits NIE and TBUE in
C1C/CIMR and the bit TBU in C14/CISR are set to high.
1
R/W
TIE
Transmit Idle Enable.
The Transmit Idle Interrupt will be enabled if both AIE(bit 15) and
TIE are set to high, otherwise, the Transmit Idle Interrupt will be
disabled. The hardware interrupt will be asserted if all of the
C1C/CIMR AIE, C1C/CIMR TIE and C14/CISR TIDLE are set to
high.
0
R/W
TINTE
Transmit Interrupt Enable.
The Transmit Interrupt will be enabled if both NIE(bit 16) and
TINTE are set to high, otherwise, the Transmit Interrupt will be
disabled. The hardware interrupt will be asserted if all of the bits
NIE and TINTE in C1C/CIMR and the bit TINI in C14/CISR are
set to high.