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參數(shù)資料
| 型號： | W89C880F |
| 英文描述： | LAN Hub Controller |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁數(shù)： | 57/72頁 |
| 文件大小： | 731K |
| 代理商： | W89C880F |
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W89C840F
Publication Release Date:April 1997
Revision A1
- 57 -
7
PTL
Packet Too Long:
When set, it indicates that the received packet length exceeds 2048 bytes. This bit
is valid only when
set
RFD (R00[9]) or RLD (R00[8]), i.e. the first or the last
descriptor of the current frame.
6
LE
Late Event:
When set, it indicates that the MAC detected a receive collision event occurred
at the time after the 64 bytes following Start Frame Delimiter (SFD) when the
MAC is receiving the packet. This bit is valid only when
set
RFD (R00[9]) or
RLD (R00[8]), i.e. the first or the last descriptor of the current frame.
3
MRE
MII Receive Error:
When set, it indicates that the a receive error
from
the physical layer was
reported during the frame reception. This bit is valid only when
set
RFD
(R00[9]) or RLD (R00[8]), i.e. the first or the last descriptor of the current frame.
2
DB
Dribbling Bit :
When set, it indicates that the receive packet contains extra bits, not aligned with
the 8 bits boundary.
The received packet will be treated as a good packet even the DB bit is set if the
CRC Error (R00[1]) is reset, i.e. no CRC error.
This bit is not valid if a late collision (R00[6]) or runt packet (R00[11]) is set.
This bit is valid only when
set
RFD (R00[9]) or RLD (R00[8]), i.e. the first or
the last descriptor of the current frame.
1
CRCE
CRC Error:
When set, it indicates that a cyclic redundancy check (CRC) error
was
occurred
on the received packet. If a MII receive error is detected during the packet
receiving, the CRC Error bit is also set even though the CRC may be correct.
This bit is valid only when
set
RFD (R00[9]) or RLD (R00[8]), i.e. the first or
the last descriptor of the current frame.
R01, Transmit Descriptor 1
The R01 is used to describe the receive control configuration for the current frame receiving.
The receive DMA state machine will fetch the first descriptor of the current frame , at first, to
decide the receive control configuration for the current receive frame. The receive DMA state machine will
also fetch each descriptor information before storing the received data to the data buffer in the host memory
described by the current descritpor.
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