
W89C840F
- 44 -
5
R/W
ABP
Accept Broadcast Packet.
When set, all incoming packet with a broadcast address
i s
accepted. When reset, the incoming packet with a broadcast address
i s
rejected. Default 1.
4
R/W
AMP
Accept Multicast Packet.
When set, all incoming packets with a multicast address match
ed
w th
the node multicast address table (MAR7 ~ MAR0)
i s
accepted. When reset, all incoming packet with a multicast address
(excluding broadcast address)
i s
rejected. Default 1.
3
R/W
APP
Accept All Physical Packet.
When set, all incoming pa
cket w th uni cast address i s
accepted. When reset, only the incoming packets with destination
address matching the physical address of the node
i s
accepted.
Default 0.
2
R
---
Reserved. Fixed at 0.
1
R/W
RXON
Receive On.
When set, the receive process start
s
(leave the Idle state, at first,
and fetch the receive descriptor according to the configuration of
the register C0C/CRDLA ).
When reset, the receive state machine
i s
stopped after the current
frame is completed.
The C0C/CRDLA, C40/PAR0, C44/PAR1, C38/MAR0 and
C3C/MAR1 registers must be programmed before setting the
RXON high.
0
R
---
Reserved. Fixed at 0.
C1C/CIMR Interrupt Mask Register
The register C1C/CIMR controls the interrupt enable corresponding to the bits in the register C14/CISR.
Bit
Attribute
Bit name
Description
31:17
R
---
Reserved. Fixed at 0.
16
R/W
NIE
Normal Interrupt Enable.
The Normal Interrupt will be enabled if the NIE is set to high.
The Normal Interrupt is disabled when the NIE is reset to low. The
hardware interrupt will be asserted if both the NIE bit of the
C1C/CIMR and the NIR bit of the C14/CISR NIR are set to high.
15
R/W
AIE
Abnormal Interrupt Enable.
The Abnormal Interrupt will be enabled if the AIE is set to high.
The Abnormal Interrupt is disabled when the AIE is reset to low.
The hardware interrupt will be asserted if both the AIE bit of the
C1C/CIMR and the AIR bit of the C14/CISR AIR are set to high.