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參數(shù)資料
| 型號(hào)： | W89C840F |
| 英文描述： | LAN NODE CONTROLLER |
| 中文描述： | 網(wǎng)絡(luò)節(jié)點(diǎn)控制器 |
| 文件頁(yè)數(shù)： | 53/72頁(yè) |
| 文件大?。?/td> | 731K |
| 代理商： | W89C840F |
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W89C840F
Publication Release Date:April 1997
Revision A1
- 53 -
23:16
R/W
PAR2
Physical Address 2.
The PAR2 defines the bit 16~23 of the MAC address.
15:8
R/W
PAR1
Physical Address 1.
The PAR1 defines the bit 8~15 of the MAC address.
7:0
R/W
PAR0
Physical Address 0.
The PAR0 defines the bit 0~7 of the MAC address.
C44/CPA1 Physical Address Register 1
The C44/CPA1 defines the last 16 bits of the 48 bits MAC address. The CPA1 value is loaded from
EEPROM after hardware reset
Bit
Attribute
Bit name
Description
31:16
R
---
Reserved. Fixed at 0.
15:8
R/W
PAR5
Physical Address 5.
The PAR5 defines the 40~47 bit of the 48 bit of the MAC address.
7:0
R/W
PAR4
Physical Address 4.
The PAR0 defines the 32~39 bit of the 48 bit of the MAC address.
C48/CBRCR Boot ROM Size Configuration Register
This register configure
s
the size of the boot ROM. The bit 0 to bit 2 of the register C48/CBRCR are loaded
from the external EEPROM after the deasserted of the hardware reset. The configuration of the BPS[2:0] will
affect the return value from the register F30/FERBA to determine how large the expansion memory space the
on-board boot ROM needs when it is read by the power-on software.
Bit
Attribute
Bit name
Description
31:3
R
---
Reserved. Fixed at 0.
2:0
R/W
BPS[2:0]
Boot ROM Size Select.
The si ze of on
board boot ROM is
determ ned
by BPS[2:0].
BPS2 BPS1 BPS0 Size
0 0 X No Boot ROM
0 1 0 8K
0 1 1 16K
1 0 0 32K
1 0 1 64K
1 1 0 128K
1 1 1 256K
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