參數(shù)資料
型號： W89C840F
英文描述： LAN NODE CONTROLLER
中文描述： 網(wǎng)絡(luò)節(jié)點控制器
文件頁數(shù)： 50/72頁
文件大?。?/td> 731K
代理商： W89C840F
W89C840F
- 50 -
3:0
R/W
EEBRD
[33:0]
EEPROM/Boot ROM Data 0 to 3:
The EEBRD[3:0] are used to store the read/write data for the on-
board boot ROM access when
reset
EESEL low.
When
set
EESEL high,
1) the EEBRD[3] reflects the input data from the BtAdata3/EEDO
pin(connected to EEPROM data output) instantly.
2) the EEBRD[2] stores the output data that will be put on the
BtAdata2/EEDI pin(connected to EEPROM data input) directly.
3) the EEBRD[1] stores t
he output data that w l l be put
on
the BtAdata1/EECK pin (EEPROM serial clock input) directly.
4) the EEBRD[0] stores t
he output data that w l l be put on
the EECS pin(connected to EEPROM chip select) directly.
For accessing the external EEPROM device, the chip select signal,
the serial clock and the data input should follow the AC
specification defined by the external EEPROM device.
C28/CBROA Boot ROM Offset Address Register
The register C28/CBROA specif
i es
the read or write address of the external boot ROM when accessing the
boot ROM through the register C24/CMIIR of the W89C840F
.
Bit
Attribute
Bit name
Description
31:18
R
---
Reserved. Fixed at 0.
17:0
R/W
BROA
Boot ROM Offset Address.
This field contains boot ROM offset address.
C2C/CGTR General Timer Register
The C2C/CGTR shows the real time content of the W89C840F‘s internal general timer
Bit
Attribute
Bit name
Description
31:17
R
---
Reserved. Fixed at 0.
16
R/W
RECUR
Recursive Mode:
If previ ousl y set RECUR hi gh, t
he state of the bit 0 to bit 15
in the register C2C/CGTR will be set to the states programmed by
the driver at the last time when the TIME timer count
down to
zero
.
Default 0.
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