參數(shù)資料
型號(hào)： W89C840F
英文描述： LAN NODE CONTROLLER
中文描述： 網(wǎng)絡(luò)節(jié)點(diǎn)控制器
文件頁(yè)數(shù)： 35/72頁(yè)
文件大?。?/td> 731K
代理商： W89C840F
W89C840F
Publication Release Date:April 1997
Revision A1
- 35 -
The following table detailedly described the function of each bit of the register C00/CBCR.
Bit
Attribute
Bit name
Description
31:22
R
---
Reserved. Fixed at 0.
21
R/W
WAIT
Wait State Insertion
When as a bus mster and WAIT are set, W89C840F
executes memory read/write with one wait state every data phase.
When
as a bus mster and WAIT are reset,
W89C840F
executes memory read/write with zero wait state every data
phase.
20
R/W
DBE
Descriptor Big Endian Mode
When set, the descriptors will be handled in big endian mode;
when reset, the descriptors will be treated in little endian mode
19:16
R
---
Reserved. Fixed at 0.
15:14
R/W
CA
Cache Alignment
CA defines the address boundary for the
burst access to the
transm tted
or receive
d
data.
When the starting address of the data burst access is not aligned,
more specifically, the starting address should be a multiple of
some number such as 4, 8 etc., the W89C840F will have the first
burst transfer that causes that the next burst access will has the
start address aligned.
After the first burst occurred, all other burst operation
s
are
aligned with the configuration of CA accordingly.
The CA must be initialized with a non zero value after reset.
The alignment configuration is as following:
[15:14] Address Alignment
-----------------------------------------------------
[00] reserved
[01] 8 long-word alignment
[10] 16 long-word alignment
[11] 32 long-word alignment
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