參數(shù)資料
型號: W83977CTF-PW
英文描述: PERIPHERAL (MULTIFUNCTION) CONTROLLER
中文描述: 周邊(多功能)控制器
文件頁數(shù): 132/161頁
文件大?。?/td> 592K
代理商: W83977CTF-PW
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-123 -
Revision A1
CRF6 (Default 0x00)
Bit 7: Reserved. Return zero when read.
Bit 6 - 0: Enable bits of the SMI#/SCI# generation due to the device's IRQ.
These bits enable the generation of an SMI#/SCI# interrupt due to any IRQ of the devices.
SMI#/SCI# logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS) or
(FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS) or (KBCIRQEN and
KBCIRQSTS) or (MOUIRQEN and MOUIRQSTS) or (URCIRQEN and URCIRQSTS) or
(WDTIRQEN and WDTIRQSTS) or (COMIRQEN and COMIRQSTS) or (GP11IRQEN and
GP11IRQSTS) or (GP10IRQEN and GP10IRQSTS)
Bit 6: URCIRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to UART C's IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to UART C's IRQ.
Bit 5: MOUIRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to MOUSE's IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to MOUSE's IRQ.
Bit 4: KBCIRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to KBC's IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to KBC's IRQ.
Bit 3: PRTIRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to printer port's IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to printer port's IRQ.
Bit 2: FDCIRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to FDC's IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to FDC's IRQ.
Bit 1: URAIRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to UART A's IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to UART A's IRQ.
Bit 0: URBIRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to UART B's IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to UART B's IRQ.
CRF7 (Default 0x00)
Bit 7 - 5: Reserved. Return zero when read.
Bit 3: Reserved. Return zero when read.
Bit 4 and Bit 2 - 0:Enable bits of the SMI#/SCI# generation due to the individual GPIO IRQ
functions.
Bit 4: WDTIRQEN.
= 0
disable the generation of an SMI#/SCI# interrupt due to watch dog timer's IRQ.
= 1
enable the generation of an SMI#/SCI# interrupt due to watch dog timer's IRQ.
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