參數(shù)資料
型號: W83977CTF-PW
英文描述: PERIPHERAL (MULTIFUNCTION) CONTROLLER
中文描述: 周邊(多功能)控制器
文件頁數(shù): 100/161頁
文件大小: 592K
代理商: W83977CTF-PW
W83977EF/ CTF
PRELIMINARY
Publication Release Date: March 1999
-91 -
Revision A1
After Power-on reset, the value on RTSA (pin 43) is latched by HEFRAS of CR26. In Compatible
PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port
address 3F0h or 370h). Secondly, an index value (02h, 07h-FFh) must be written to the Extended
Functions Index Register (I/O port address 3F0h or 370h, the same as the Extended Functions
Enable Register) to identify which configuration register is to be accessed. The designer can then
access the desired configuration register through the Extended Functions Data Register (I/O port
address 3F1h or 371h).
After programming of the configuration register is finished, an additional value (AAh) should be
written to EFERs to exit the Extended Function mode, to prevent unintentional access to these
configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the
configuration registers against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
8.1.2 Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83977EF/CTF enters the default operating mode. Before the
W83977EF/CTF enters the extended function mode, a specific value must be programmed into the
Extended Function Enable Register (EFER) so that the extended function register can be accessed.
The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port
addresses are 3F0h or 370h (as described in previous section).
8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data
Registers(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration
Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function
Data Register (EFDR). The EFIRs are write-only registers with port address 3F0h or 370h (as
described in section 8.1.1) on PC/AT systems; the EFDRs are read/write registers with port address
3F1h or 371h (as described in section 8.1.1) on PC/AT systems.
8.2 Configuration Sequence
To program W83977ATF configuration registers, the following configuration sequence must be
followed:
(1). Enter the extended function mode
(2). Configure the configuration registers
(3). Exit the extended function mode
8.2.1 Enter the extended function mode
To place the chip into the extended function mode, two successive writes of 0x87 must be applied to
Extended Function Enable Registers (EFERs, i.e. 3F0h or 370h).
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